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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
PD703100-33, 703100-40, 703101-33, 703102-33
V850E/MS1 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
TM
The PD703101-33 and PD703102-33 are members of the V850 FamilyTM of 32-bit single-chip microcontrollers designed for real-time control operations. These microcontrollers provide on-chip features, including a 32-bit CPU core, ROM, RAM, interrupt controller, real-time pulse unit, serial interface, A/D converter, and DMA controller. The PD703100-33 and PD703100-40 are ROM-less versions of the PD703101-33 and PD703102-33 products. The PD703100-A33, PD703100-A40, PD703101-A33, and PD703102-A33 are also available as products having a 3.3-V power supply for external pins. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. V850E/MS1 User's Manual Hardware: U12688E V850E/MS1 User's Manual Architecture: U12197E
FEATURES
* Number of instructions: 81 * Minimum instruction execution time 25 ns (@ 40-MHz operation) ***** PD703100-40 30 ns (@ 33-MHz operation) ***** PD703100-33, 703101-33, 703102-33 * General registers 32 bits x 32 * Instruction set optimized for control applications * Internal memory ROM : None (PD703100-33, 703100-40), 96 Kbytes (PD703101-33), 128 Kbytes (PD703102-33) RAM : 4 Kbytes * Advanced on-chip interrupt controller * Real-time pulse unit suitable for control operations * Powerful serial interface (on-chip dedicated baud rate generator) * On-chip clock generator * 10-bit resolution A/D converter: 8 channels * DMA controller: 4 channels * Power saving functions
APPLICATIONS
* Office automation equipment: printers, facsimile machines, PPCs, etc. * Multimedia equipment: digital still cameras, video printers, etc. * Consumer equipment: single-lens reflex cameras, etc. * Industrial equipment: motor controllers, NC machine tools, etc.
The information in this document is subject to change without notice.
Document No. U13995EJ1V0DS00 (1st edition) Date Published April 1999 N CP(K) Printed in Japan
(c)
1999
PD703100-33, 703100-40, 703101-33, 703102-33
ORDERING INFORMATION
Maximum Operating Frequency (MHz) 33 MHz 40 MHz 33 MHz 33 MHz Internal ROM (bytes) None None 96 Kbytes 128 Kbytes
Part Number
Package 144-pin plastic LQFP (fine pitch) (20 x 20 mm) 144-pin plastic LQFP (fine pitch) (20 x 20 mm) 144-pin plastic LQFP (fine pitch) (20 x 20 mm) 144-pin plastic LQFP (fine pitch) (20 x 20 mm)
PD703100GJ-33-8EU PD703100GJ-40-8EU PD703101GJ-33-xxx-8EU PD703102GJ-33-xxx-8EU
Remark xxx indicates ROM code suffix.
PIN CONFIGURATION (Top view)
144-pin plastic LQFP (fine pitch) (20 x 20 mm) * PD703100GJ-33-8EU * PD703100GJ-40-8EU * PD703101GJ-33-xxx-8EU * PD703102GJ-33-xxx-8EU
INTP103/DMARQ3/P07 INTP102/DMARQ2/P06 INTP101/DMARQ1/P05 INTP100/DMARQ0/P04 TI10/P03 TCLR10/P02 TO101/P01 TO100/P00 VSS INTP113/DMAAK3/P17 INTP112/DMAAK2/P16 INTP111/DMAAK1/P15 INTP110/DMAAK0/P14 TI11/P13 TCLR11/P12 TO111/P11 TO110/P10 INTP123/TC3/P107 INTP122/TC2/P106 INTP121/TC1/P105 INTP120/TC0/P104 TI12/P103 TCLR12/P102 TO121/P101 TO120/P100 ANI7/P77 ANI6/P76 ANI5/P75 ANI4/P74 ANI3/P73 ANI2/P72 ANI1/P71 ANI0/P70 AVDD AVSS AVREF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 142 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
VDD D0/P40 D1/P41 D2/P42 D3/P43 D4/P44 D5/P45 D6/P46 D7/P47 VSS D8/P50 D9/P51 D10/P52 D11/P53 D12/P54 D13/P55 D14/P56 D15/P57 HVDD A0/PA0 A1/PA1 A2/PA2 A3/PA3 A4/PA4 A5/PA5 A6/PA6 A7/PA7 VSS A8/PB0 A9/PB1 A10/PB2 A11/PB3 A12/PB4 A13/PB5 A14/PB6 A15/PB7
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
A16/P60 A17/P61 A18/P62 A19/P63 A20/P64 A21/P65 A22/P66 A23/P67 HVDD CS0/RAS0/P80 CS1/RAS1/P81 CS2/RAS2/P82 CS3/RAS3/P83 CS4/RAS4/IOWR/P84 CS5/RAS5/IORD/P85 CS6/RAS6/P86 CS7/RAS7/P87 LCAS/LWR/P90 UCAS/UWR/P91 RD/P92 WE/P93 BCYST/P94 OE/P95 HLDAK/P96 HLDRQ/P97 VSS REFRO/PX5 WAIT/PX6 CLKOUT/PX7 TO150/P120 TO151/P121 TCLR15/P122 TI15/P123 INTP150/P124 INTP151/P125 INTP152/P126
2
NMI/P20 P21 TXD0/SO0/P22 RXD0/SI0/P23 SCK0/P24 TXD1/SO1/P25 RXD1/SI1/P26 SCK1/P27 VDD INTP133/SCK2/P37 INTP132/SI2/P36 INTP131/SO2/P35 INTP130/P34 TI13/P33 TCLR13/P32 TO131/P31 TO130/P30 INTP143/SCK3/P117 INTP142/SI3/P116 INTP141/SO3/P115 INTP140/P114 TI14/P113 TCLR14/P112 TO141/P111 TO140/P110 CVDD X2 X1 CVSS CKSEL MODE0 MODE1 MODE2 MODE3 RESET INTP153/ADTRG/P127
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
PIN NAMES
A0 to A23 ADTRG ANI0 to ANI7 AVDD AVREF AVSS BCYST CKSEL CLKOUT CS0 to CS7 CVDD CVSS D0 to D15 : Address Bus : AD Trigger Input : Analog Input : Analog Power Supply : Analog Reference Voltage : Analog Ground : Bus Cycle Start Timing : Clock Generator Operating Mode Select : Clock Output : Chip Select : Clock Generator Power Supply : Clock Generator Ground : Data Bus P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P107 P110 to P117 P120 to P127 PA0 to PA7 PB0 to PB7 PX5 to PX7 RAS0 to RAS7 RD REFRQ RESET RXD0, RXD1 SCK0 to SCK3 SI0 to SI3 SO0 to SO3 TC0 to TC3 TI10 to TI15 TO100, TO101, TO110, TO111, : I/O Read Strobe : I/O Write Strobe : Lower Column Address Strobe : Lower Write Strobe : Mode : Non-Maskable Interrupt Request : Output Enable : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 TO120, TO121, TO130, TO131, TO140, TO141, TO150, TO151 TXD0, TXD1 UCAS UWR VDD VSS WAIT WE X1, X2 : Transmit Data : Upper Column Address Strobe : Upper Write Strobe : Power Supply for Internal Unit : Ground : Wait : Write Enable : Crystal : Port 5 : Port 6 : Port 7 : Port 8 : Port 9 : Port 10 : Port 11 : Port 12 : Port A : Port B : Port X : Row Address Strobe : Read : Refresh Request : Reset : Receive Data : Serial Clock : Serial Input : Serial Output : Terminal Count Signal : Timer Input : Timer Output
DMAAK0 to DMAAK3 : DMA Acknowledge DMARQ0 to DMARQ3 : DMA Request HLDAK HLDRQ HVDD INTP110 to INTP113, INTP120 to INTP123, INTP130 to INTP133, INTP140 to INTP143, INTP150 to INTP153 IORD IOWR LCAS LWR MODE0 to MODE3 NMI OE P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 : Hold Acknowledge : Hold Request : Power Supply for External Pins
INTP100 to INTP103, : Interrupt Request from Peripherals
TCLR10 to TCLR15 : Timer Clear
Preliminary Data Sheet U13995EJ1V0DS00
3
PD703100-33, 703100-40, 703101-33, 703102-33
INTERNAL BLOCK DIAGRAM
NMI INTP100 to INTP103, INTP110 to INTP113, INTP120 to INTP123, INTP130 to INTP133, INTP140 to INTP143, INTP150 to INTP153 ROM INTC Instruction queue Note PC TO100, TO101, TO110, TO111, TO120, TO121, TO130, TO131, TO140, TO141, TO150, TO151 TCLR10 to TCLR15 TI10 to TI15 4 Kbytes Barrel shifter RPU RAM System registers Multiplier (32 x 32 64) DRAMC CPU BCU HLDRQ HLDAK CS0 to CS7/RAS0 to RAS7 IOWR IORD REFRQ BCYST WE RD Page ROM controller OE UWR/UCAS LWR/LCAS General registers (32 bits x 32) ALU DMAC SIO SO0/TXD0 SI0/RXD0 SCK0 UART0/CSI0 WAIT A0 to A23 D0 to D15 DMARQ0 to DMARQ3 DMAAK0 to DMARQ3 TC0 to TC3
BRG0 SO1/TXD1 SI1/RXD1 SCK1 CKSEL CLKOUT CG
P120 to P127 P110 to P117 P100 to P107 P90 to P97 P80 to P87 P70 to P77 P60 to P67 P50 to P57 P40 to P47 P30 to P37 P21 to P27 P10 to P17 PX5 to PX7 PB0 to PB7 PA0 to PA7 P00 to P07 HVDD P20
UART1/CSI1
Port
X1 X2 CVDD CVSS
BRG1 SO2 SI2 SCK2
CSI2
BRG2 SO3 SI3 SCK3
System controller
MODE0 to MODE3 RESET
CSI3
VDD ANI0 to ANI7 AVREF AVSS AVDD ADTRG ADC VSS
Note PD703100-33, 703100-40: None PD703101-33: 96 Kbytes (mask ROM)
PD703102-33: 128 Kbytes (mask ROM)
4
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
CONTENTS
1. 2.
DIFFERENCES AMONG PRODUCTS........................................................................................... PIN FUNCTIONS ............................................................................................................................. 2.1 2.2 2.3 Port Pins ................................................................................................................................. Non-port Pins ......................................................................................................................... Pin I/O Circuits and Recommended Connection of Unused Pins.....................................
7 8 8 11 15 18 18
18 18 18 19 19 19 19 19 19 19
3.
FUNCTION BLOCKS ...................................................................................................................... 3.1 Internal Units ..........................................................................................................................
3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 3.1.9 CPU ........................................................................................................................................... Bus control unit (BCU) ............................................................................................................... ROM .......................................................................................................................................... RAM........................................................................................................................................... Ports .......................................................................................................................................... Interrupt controller (INTC).......................................................................................................... Clock generator (CG)................................................................................................................. Real-time pulse unit (RPU) ........................................................................................................ Serial interface (SIO) .................................................................................................................
3.1.10 A/D converter (ADC) ..................................................................................................................
4. 5. 6.
CPU FUNCTIONS............................................................................................................................ BUS CONTROL FUNCTIONS........................................................................................................ MEMORY ACCESS CONTROL FUNCTIONS .............................................................................. 6.1 6.2 SRAM Connection.................................................................................................................. Page ROM Controller (ROMC) ..............................................................................................
6.2.1 6.2.2 Features..................................................................................................................................... Page ROM connection............................................................................................................... Features..................................................................................................................................... DRAM Connections ...................................................................................................................
20 20 21 21 22
22 22
6.3
DRAM Controller ....................................................................................................................
6.3.1 6.3.2
24
24 24
7. 8.
DMA FUNCTIONS (DMA CONTROLLER) ................................................................................... INTERRUPT/EXCEPTION PROCESSING FUNCTIONS............................................................... 8.1 Features ..................................................................................................................................
26 28 28 33 34 5
9.
CLOCK GENERATION FUNCTIONS ............................................................................................
10. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT).....................................................
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
11. SERIAL INTERFACE FUNCTION .................................................................................................. 11.1 Asynchronous Serial Interfaces 0, 1 (UART0, UART1)....................................................... 11.2 Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3) ................................................................... 11.3 Dedicated Baud Rate Generators 0 to 2 (BRG0 to BRG2).................................................. 37 37 38 40
12. A/D CONVERTER............................................................................................................................ 41 13. PORT FUNCTIONS ......................................................................................................................... 42 14. RESET FUNCTION .......................................................................................................................... 53 15. INSTRUCTION SET ......................................................................................................................... 54 16. ELECTRICAL SPECIFICATIONS (PRELIMINARY VALUES)...................................................... 64 17. PACKAGE DRAWING ..................................................................................................................... 120 18. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 121
6
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
1. DIFFERENCES AMONG PRODUCTS
Product Name Item Internal ROM -33 None
PD703100
-40 -A33 -A40
PD703101
-33 -A33
PD703102
-33 -A33
PD70F3102
-33 -A33
96 Kbytes (mask ROM) 40 MHz 33 MHz 40 MHz 33 MHz
128 Kbytes (mask ROM)
128 Kbytes (flash memory)
Maximum operating frequency HVDD
33 MHz
4.5 to 5.5 V
3.0 to 3.6 V
4.5 to 5.5 V
3.0 to 3.6 V
4.5 to 5.5 V
3.0 to 3.6 V
4.5 to 5.5 V
3.0 to 3.6 V
Operation mode Single-chip mode 0, 1 Flash memory programming mode Flash memory programming pin Electrical specifications Package None Provided
None
Provided
None
Provided (VPP)
Power consumptions differ (refer to the data sheet of each product).
144LQFP
144LQFP 157FBGA
144LQFP
144LQFP 157FBGA
144LQFP
144LQFP 157FBGA
144LQFP
144LQFP 157FBGA
Others
Noise tolerance and noise radiation will differ due to the differences in circuit scale and mask layout.
Remark 144LQFP: 144-pin plastic LQFP (fine pitch) (20 x 20 mm) 157FBGA: 157-pin plastic FBGA (14 x 14 mm)
Preliminary Data Sheet U13995EJ1V0DS00
7
PD703100-33, 703100-40, 703101-33, 703102-33
2. PIN FUNCTIONS 2.1 Port Pins
(1/3)
Pin Name P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47 I/O Port 4 8-bit I/O port Input/output mode can be specified in 1-bit units I/O Port 3 8-bit I/O port. Input/output mode can be specified in 1-bit units I I/O Port 2 P20 is an input only port. When a valid edge is input, this pin operates as NMI input. Also, bit 0 of the P2 register indicates the NMI input status. P21 to P27 are 7-bit I/O port. Input/output mode can be specified in 1-bit units I/O Port 1 8-bit I/O port Input/output mode can be specified in 1-bit units I/O I/O Function Port 0 8-bit I/O port Input/output mode can be specified in 1-bit units Alternate Function TO100 TO101 TCLR10 TI10 INTP100/DMARQ0 INTP101/DMARQ1 INTP102/DMARQ2 INTP103/DMARQ3 TO110 TO111 TCLR11 TI11 INTP110/DMAAK0 INTP111/DMAAK1 INTP112/DMAAK2 INTP113/DMAAK3 NMI - TXD0/SO0 RXD0/SO0 SCK0 TXD1/SO1 RXD1/SI1 SCK1 TO130 TO131 TCLR13 TI13 INTP130 INTP131/SO2 INTP132/SI2 INTP133/SCK2 D0 to D7
8
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(2/3)
Pin Name P50 to P57 I/O I/O Function Port 5 8-bit I/O port Input/output mode can be specified in 1-bit units Port 6 8-bit I/O port Input/output mode can be specified in 1-bit units Port 7 8-bit input only port Port 8 8-bit I/O port Input/output mode can be specified in 1-bit units Alternate Function D8 to D15
P60 to P67
I/O
A16 to A23
P70 to P77
I
ANI0 to ANI7
P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 P100 P101 P102 P103 P104 P105 P106 P107 P110 P111 P112 P113 P114 P115 P116 P117
I/O
CS0/RAS0 CS1/RAS1 CS2/RAS2 CS3/RAS3 CS4/RAS4/IOWR CS5/RAS5/IORD CS6/RAS6 CS7/RAS7
I/O
Port 9 8-bit I/O port Input/output mode can be specified in 1-bit units
LCAS/LWR UCAS/UWR RD WE BCYST OE HLDAK HLDRQ
I/O
Port 10 8-bit I/O port Input/output mode can be specified in 1-bit units
TO120 TO121 TCLR12 TI12 INTP120/TC0 INTP121/TC1 INTP122/TC2 INTP123/TC3
I/O
Port 11 8-bit I/O port Input/output mode can be specified in 1-bit units
TO140 TO141 TCLR14 TI14 INTP140 INTP141/SO3 INTP142/SI3 INTP143/SCK3
Preliminary Data Sheet U13995EJ1V0DS00
9
PD703100-33, 703100-40, 703101-33, 703102-33
(3/3)
Pin Name P120 P121 P122 P123 P124 P125 P126 P127 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PX5 PX6 PX7 I/O Port X 3-bit I/O port Input/output mode can be specified in 1-bit units I/O Port B 8-bit I/O port Input/output mode can be specified in 1-bit units I/O Port A 8-bit I/O port Input/output mode can be specified in 1-bit units I/O I/O Function Port 12 8-bit I/O port Input/output mode can be specified in 1-bit units Alternate Function TO150 TO151 TCLR15 TI15 INTP150 INTP151 INTP152 INTP153/ADTRG A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 REFRQ WAIT CLKOUT
10
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
2.2 Non-port Pins
(1/4)
Pin Name TO100 TO101 TO110 TO111 TO120 TO121 TO130 TO131 TO140 TO141 TO150 TO151 TCLR10 TCLR11 TCLR12 TCLR13 TCLR14 TCLR15 TI10 TI11 TI12 TI13 TI14 TI15 INTP100 INTP101 INTP102 INTP103 INTP110 INTP111 INTP112 INTP113 INTP120 INTP121 INTP122 INTP123 I External maskable interrupt request input, shared as external capture trigger input for timer 12 I External maskable interrupt request input, shared as external capture trigger input for timer 11 I External maskable interrupt request input, shared as external capture trigger input for timer 10 I External count clock input for timers 10 to 15 I External clear signal input for timers 10 to 15 I/O O Function Pulse signal output for timers 10 to 15 Alternate Function P00 P01 P10 P11 P100 P101 P30 P31 P110 P111 P120 P121 P02 P12 P102 P32 P112 P122 P03 P13 P103 P33 P113 P123 P04/DMARQ0 P05/DMARQ1 P06/DMARQ2 P07/DMARQ3 P14/DMAAK0 P15/DMAAK1 P16/DMAAK2 P17/DMAAK3 P104/TC0 P105/TC1 P106/TC2 P107/TC3
Preliminary Data Sheet U13995EJ1V0DS00
11
PD703100-33, 703100-40, 703101-33, 703102-33
(2/4)
Pin Name INTP130 INTP131 INTP132 INTP133 INTP140 INTP141 INTP142 INTP143 INTP150 INTP151 INTP152 INTP153 SO0 SO1 SO2 SO3 SI0 SI1 SI2 SI3 SCK0 SCK1 SCK2 SCK3 TXD0 TXD1 RXD0 RXD1 D0 to D7 D8 to D15 A0 to A7 A8 to A15 A16 to A23 LWR UWR RD WE OE O O O O O Lower byte write-enable signal output for external data bus Higher byte write-enable signal output for external data bus Read strobe signal output for external data bus Write enable signal output for DRAM Output enable signal output for DRAM O 24-bit address bus for external memory I/O 16-bit data bus for external memory I Serial receive data input for UART0 and UART1 O Serial transmit data output for UART0 and UART1 I/O Serial clock I/O (3-wire) for CSI0 to CSI3 I Serial receive data input (3-wire) for CSI0 to CSI3 O Serial transmit data output (3-wire) for CSI0 to CSI3 I External maskable interrupt request input, shared as external capture trigger input for timer 15 I External maskable interrupt request input, shared as external capture trigger input for timer 14 I/O I Function External maskable interrupt request input, shared as external capture trigger input for timer 13 Alternate Function P34 P35/SO2 P36/SI2 P37/SCK2 P114 P115/SO3 P116/SI3 P117/SCK3 P124 P125 P126 P127/ADTRG P22/TXD0 P25/TXD1 P35/INTP131 P115/INTP141 P23/RXD0 P26/RXD1 P36/INTP132 P116/INTP142 P24 P27 P37/INTP133 P117/INTP143 P22/SO0 P25/SO1 P23/SI0 P26/SI1 P40 to P47 P50 to P57 PA0 to PA7 PB0 to PB7 P60 to P67 P90/LCAS P91/UCAS P92 P93 P95
12
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(3/4)
Pin Name LCAS UCAS RAS0 to RAS3 RAS4 RAS5 RAS6 RAS7 BCYST CS0 to CS3 O O Strobe signal output indicating start of bus cycle Chip select signal output I/O O O O Function Column address strobe signal output for DRAM's lower data Column address strobe signal output for DRAM's higher data Low address strobe signal output for DRAM Alternate Function P90/LWR P91/UWR P80/CS0 to P83/CS3 P84/CS4/IOWR P85/CS5/IORD P86/CS6 P87/CS7 P94 P80/RAS0 to P83/RAS3 P84/RAS4/IOWR P85/RAS5/IORD P86/RAS6 P87/RAS7 I O O O I Control signal input for inserting waits in bus cycle Refresh request signal output for DRAM DMA write strobe signal output DMA read strobe signal output DMA request signal input PX6 PX5 P84/RAS4/CS4 P85/RAS5/CS5 P04/INTP100 to P07/INTP103 P14/INTP110 to P17/INTP113 P104/INTP120 to P107/INTP123 P96 P97 P70 to P77 P20 PX7 - -
CS4 CS5 CS6 CS7 WAIT REFRQ IOWR IORD DMARQ0 to DMARQ3 DMAAK0 to DMAAK3 TC0 to TC3
O
DMA acknowledge signal output
O
DMA end (terminal count) signal output
HLDAK HLDRQ ANI0 to ANI7 NMI CLKOUT CKSEL MODE0 to MODE3 RESET X1 X2 ADTRG AVREF AVDD AVSS
O I I I O I I
Bus hold acknowledge output Bus hold request input Analog input to A/D converter Non-maskable interrupt request input System clock output Input for specifying clock generator's operation mode Specify operation modes
I I - I I - -
System reset input Oscillator connection for system clock. Input is via X1 when using an external clock. A/D converter external trigger input Reference voltage input for A/D converter Positive power supply for A/D converter Ground potential for A/D converter
- - - P127/INTP153 - - -
Preliminary Data Sheet U13995EJ1V0DS00
13
PD703100-33, 703100-40, 703101-33, 703102-33
(4/4)
Pin Name CVDD CVSS VDD HVDD VSS I/O - - - - - Function Positive power supply for dedicated clock generator Ground potential for dedicated clock generator Positive power supply (power supply for internal units) Positive power supply (power supply for external pins) Ground potential Alternate Function - - - - -
14
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the I/O circuit type of each pin and recommended connection of unused pins. Figure 2-1 shows the various circuit types using partially abridged diagrams. When connecting to VDD or VSS via a resistor, a resistance value in the range of 1 to 10 k is recommended. Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (1/2)
Pin P00/TO100, P01/TO101 P02/TCLR10, P03/TI10 P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3 P10/TO110, P11/TO111 P12/TCLR11, P13/TI11 P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3 P20/NMI P21 P22/TXD0/SO0 P23/RXD0/SI0 P24/SCK0 P25/TXD1/SO1 P26/RXD1/SI1 P27/SCK1 P30/TO130, P31/TO131 P32/TCLR13,P33/TI13 P34/INTP130 P35/INTP131/SO2 P36/INTP132/SI2 P37/INTP133/SCK2 P40/D0 to P47/D7 P50/D8 to P57/D15 P60/A16 to P67/A23 P70/ANI0 to P77/ANI7 P80/CS0/RAS0 to P83/CS3/RAS3 P84/CS4/RAS4/IOWR, P85/CS5/RAS5/IORD P86/CS6/RAS6, P87/CS7/RAS7 P90/LCAS/LWR P91/UCAS/UWR 9 5 Connect directly to VSS Input : Independently connect to HVDD or VSS via a resistor Output: Leave open 5 5 5-K 5 5-K 5-K 2 5 Connect directly to VSS Input : Independently connect to HVDD or VSS via a resistor Output: Leave open 5 5-K I/O Circuit Type 5 5-K Recommended Connection of Unused Pins Input : Independently connect to HVDD or VSS via a resistor Output: Leave open
Preliminary Data Sheet U13995EJ1V0DS00
15
PD703100-33, 703100-40, 703101-33, 703102-33
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (2/2)
Pin P92/RD P93/WE P94/BCYST P95/OE P96/HLDAK P97/HLDRQ P100/TO120, P101/TO121 P102/TCLR12, P103/TI12 P104/INTP120/TC0 to P107/INTP123/TC3 P110/TO140, P111/TOI41 P112/TCLR14, P113/TI14 P114/INTP140 P115/INTP141/SO3 P116/INTP142/SI3 P117/INTP143/SCK3 P120/TO150, P121/TO151 P122/TCLR15, P123/TI15 P124/INTP150 to P126/INTP152 P127/INTP153/ADTRG PA0/A0-PA7/A7 PB0/A8-PB7/A15 PX5/REFRQ PX6/WAIT PX7/CLKOUT CKSEL RESET MODE0 to MODE2 MODE3 AVREF, AVSS AVDD - - Connect to VSS via a resistor (RVPP) Connect directly to VSS Connect directly to HVDD 1 2 Connect directly to HVDD - 5 5 5-K 5 5-K 5-K I/O Circuit Type 5 Recommended Connection of Unused Pins Input : Independently connect to HVDD or VSS via a resistor Output: Leave open
16
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 2-1. Pin I/O Circuits
Type 1 Type 5-K VDD VDD data P-ch IN output disable N-ch N-ch P-ch IN/OUT
input enable
Type 2
Type 9
P-ch IN IN N-ch + - Comparator
VREF (threshold voltage)
input enable Schmitt trigger input with hysteresis characteristics Type 5 VDD data P-ch IN/OUT output disable N-ch
input enable
Caution Replace VDD by HVDD when referencing the circuit diagrams shown above.
Preliminary Data Sheet U13995EJ1V0DS00
17
PD703100-33, 703100-40, 703101-33, 703102-33
3. FUNCTION BLOCKS 3.1 Internal Units
3.1.1 CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits x 16 bits 32 bits, or 32 bits x 32 bits 64 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions. 3.1.2 Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory area and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an internal instruction queue of the CPU. The BCU contains DRAM controller (DRAMC), page ROM controller, and DMA controller (DMAC). (a) DRAM controller (DRAMC) The DRAM controller generates the RAS, UCAS, and LCAS signals (2CAS control) and controls access to the DRAM. It supports high-speed page DRAM and EDO DRAM, and has two types of cycles for accessing DRAM. These types of cycles are referred to as normal access (off-page) and page access (on-page). The DRAM controller also has a refresh function that is associated with the CBR refresh cycle. (b) Page ROM controller The page ROM controller supports access to ROM that has the page access function. It compares the address with that of the preceding bus cycle and controls the waits for normal access (offpage) and page access (on-page). The page ROM controller can support page sizes of 8 to 64 bytes. (c) DMA controller (DMAC) The DMA controller transfers data between memory and an I/O device in place of the CPU. The two address modes are flyby (one-cycle) transfer and two-cycle transfer. The three bus modes are single transfer, single-step transfer, and block transfer. 3.1.3 ROM The PD703101-33 contains 96-Kbytes mask ROM, and the PD703102-33 contains 128-Kbytes mask ROM. The CPU can access ROM in one clock cycle when an instruction is fetched. When single-chip mode 0 is set, ROM is mapped to the address space starting at 00000000H. When single-chip mode 1 is set, ROM is mapped to the address space starting at 00100000H. When ROM-less mode 0 or 1 is set, ROM cannot be accessed. The PD703100-33 and PD703100-40 have no internal ROM.
18
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
3.1.4 RAM RAM is mapped to the 4-Kbyte address space starting at FFFFE000H. The CPU can access RAM in one clock cycle when an instruction is fetched or data is accessed. 3.1.5 Ports In addition to the 123 pins (ports 0 to 12, A, B, and X) comprising I/O ports (of which nine pins comprise an inputonly port), various port pin and control pin functions can be selected for these pins. 3.1.6 Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP100 to INTP103, INTP110 to INTP113, INTP120 to INTP123, INTP130 to INTP133, INTP140 to INTP143, and INTP150 to INTP153) from on-chip peripheral I/O and external hardware. Eight interrupt priority levels can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. 3.1.7 Clock generator (CG) A frequency of five times (using an on-chip PLL) or one-half times (not using an on-chip PLL) that of the input clock (fXX) is supplied as the internal system clock (). Either an external oscillator is connected to pins X1 and X2 (only when the on-chip PLL synthesizer is used) or an external clock is input from the X1 pin as the input clock. 3.1.8 Real-time pulse unit (RPU) The RPU includes a six-channel 16-bit timer/event counter and a two-channel 16-bit interval timer, which enables measurement of pulse intervals and frequency as well as programmable pulse output. 3.1.9 Serial interface (SIO) Four channels are comprised of two kinds of serial interfaces: an asynchronous serial interface (UART) and a clocked serial interface (CSI). Two of these four channels are switchable between the UART and CSI and the other two channels are fixed as CSI. For UART, data is transferred via the TXD and RXD pins. For CSI, data is transferred via the SO, SI, and SCK pins. The serial clock source can be selected from dedicated baud rate generator output or the internal system clock. 3.1.10 A/D converter (ADC) This is a high-speed, high-resolution 10-bit A/D converter that includes eight analog input pins. It converts using the successive approximation method.
Preliminary Data Sheet U13995EJ1V0DS00
19
PD703100-33, 703100-40, 703101-33, 703102-33
4. CPU FUNCTIONS
{ RISC-based architecture { Uses five-stage pipeline control to enable single-clock execution of almost all instructions { Minimum instruction execution time { Memory space 25 ns (@ 40-MHz operation) ... PD703100-40 30 ns (@ 33-MHz operation) ... PD703100-33, 703101-33, 703102-33 Program space : 64-Mbyte linear Data space { General registers 32 bits x 32 { Internal 32-bit architecture { 5-stage pipeline control { Multiply/divide instructions { Saturated operation instructions { 32-bit shift instruction: 1 clock { Long/short format { Four types of bit manipulation instructions * * * * Set Clear Not Test : 4-Gbyte linear
5. BUS CONTROL FUNCTIONS
{ 16-bit/8-bit data bus sizing function { 8-space chip select output function { Wait functions * * Programmable wait function for up to seven states for each memory block External wait function using WAIT pin
{ Idle state insertion function { Bus mastering arbitration function { Bus hold function { Alternate function for port pins are connectable to external bus
20
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
6. MEMORY ACCESS CONTROL FUNCTIONS 6.1 SRAM Connection
The following figure shows an SRAM connection example. Figure 6-1. SRAM Connection Example
A1 to A17 D0 to D7 D8 to D15 CSn UWR LWR RD HVDD V850E/MS1 5V 5V WE OE VCC 1-Mbit (128 K x 8) SRAM A0 to A16 I/O1 to I/O8 CS A0 to A16 I/O1 to I/O8
CS
WE OE 5V VCC 1-Mbit (128 K x 8) SRAM
Remark n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
21
PD703100-33, 703100-40, 703101-33, 703102-33
6.2 Page ROM Controller (ROMC)
The page ROM controller (ROMC) supports access to ROM (page ROM) that has the page access function. It compares the address with that of the preceding bus cycle and performs wait control for normal access (offpage) and page access (on-page). The page ROM controller can support page widths of 8 to 64 bytes. 6.2.1 Features { Can be connected directly to 8-bit or 16-bit page ROM { For 16-bit bus width, it supports 4-, 8-, 16-, or 32-word page access For 8-bit bus width, it supports 8-, 16-, 32-, or 64-word page access { Enables waits to be set (0 to 7 waits) independently for off-page and on-page access 6.2.2 Page ROM connection The following figure shows page ROM connection examples. Figure 6-2. Page ROM Connection Examples (1/2) (a) 16-Mbit (1 M x 16) page ROM
A1 to A20
A0 to A19
D0 to D15
O1 to O16
RD CSn VDD
OE CE
WORD/BYTE 16-Mbit (1 M x 16) page ROM V850E/MS1
Remark n = 0 to 7
22
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 6-2. Page ROM Connection Examples (2/2) (b) 16-Mbit (2 M x 8) page ROM
A1 to A20
A0 to A19
D0 to D7
O0 to O7
RD CSn
OE CE
D8 to D15
WORD/BYTE 16-Mbit (2 M x 8) page ROM
V850E/MS1
A0 to A19
O0 to O7
OE CE
WORD/BYTE 16-Mbit (2 M x 8) page ROM
Remark n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
23
PD703100-33, 703100-40, 703101-33, 703102-33
6.3 DRAM Controller
6.3.1 Features { Generates the RAS, UCAS, and LCAS signals { Can be connected directly to high-speed page DRAM and EDO DRAM { Supports RAS hold mode { Can assign 4 types of DRAM to 8 memory block spaces { Supports 2CAS type DRAM { Can be switched between row and column address multiplex widths { Can insert waits (0 to 3 waits) at each of the following timings * * * * Row address pre-charge wait Row address hold wait Data access wait Column address pre-charge wait
{ Supports CBR refresh and CBR self refresh 6.3.2 DRAM Connections The following figure shows DRAM connection examples. Figure 6-3. DRAM Connection Examples (1/2) (a) 16-Mbit (1 M x 16) DRAM
A1 to A10
A0 to A9
D0 to D15
I/O1 to I/O16
RASn LCAS UCAS WE OE
RASn LCAS UCAS WE OE
V850E/MS1
16-Mbit (1 M x 16) DRAM
Remark n = 0 to 7
24
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 6-3. DRAM Connection Examples (2/2) (b) 4-Mbit (1 M x 4) DRAM
A1 to A10 D0 to D7 D8 to D15 RASn LCAS UCAS WE OE V850E/MS1
A0 to A9 I/O1 to I/O4
A0 to A9 I/O1 to I/O4
RAS CAS
RAS CAS
WE OE 4-Mbit (1 M x 4) DRAM
WE OE 4-Mbit (1 M x 4) DRAM
A0 to A9 I/O1 to I/O4
A0 to A9 I/O1 to I/O4
RAS CAS
RAS CAS
WE OE 4-Mbit (1 M x 4) DRAM
WE OE 4-Mbit (1 M x 4) DRAM
Remark n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
25
PD703100-33, 703100-40, 703101-33, 703102-33
7. DMA FUNCTIONS (DMA CONTROLLER)
{ 4 independent DMA channels { Transfer units: 8 or 16 bits
16 { Maximum transfer count: 65536 (2 )
{ Two types of transfer * * * * * * * * * * Flyby (one-cycle) transfer Two-cycle transfer Single transfer mode Single-step transfer mode Block transfer mode DMARQ0 to DMARQ3 pin (x 4) Requests from on-chip peripheral I/O (serial interface and real-time pulse unit) Requests by software Memory to I/O and vice versa Memory to memory and vice versa
{ Three transfer modes
{ Transfer requests
{ Transfer objects
{ DMA transfer end output signal (TC0 to TC3)
26
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 7-1. DMA Function Block Diagram
Internal RAM
Internal peripheral I/O
Internal bus Internal peripheral I/O bus CPU
Data control
Address control
DMA source address register (DSAnH/DSAnL) DMA destination address register (DDAnH/DDAnL)
TCn
Count control
DMA byte count register (DBCn) DMA addressing control register (DADCn)
NMI INTPmn Request from on-chip peripheral I/O DMARQn DMAAKn
DMA channel control register (DCHCn) Channel control DMA disable status register (DDISn) DMA restart register (DRSTn) DMA trigger source register (DTFRn) DMAC Bus interface V850E/MS1 External bus
External I/O
External RAM
External ROM
Remark m = 10 to 15, n=0 to 3
Preliminary Data Sheet U13995EJ1V0DS00
27
PD703100-33, 703100-40, 703101-33, 703102-33
8. INTERRUPT/EXCEPTION PROCESSING FUNCTIONS 8.1 Features
{ Interrupts * * * * * * * * Non-maskable interrupt: 1 source Maskable interrupt : 47 sources 8-level programmable priority control Multiple interrupt control based on priority levels Mask specification for each maskable interrupt request Noise elimination, edge detection, and valid edge specification for external interrupt requests Software exceptions: 32 sources Exception trap : 1 source (invalid instruction code exception)
{ Exceptions
28
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 8-1. Interrupt Control Function Block Diagram
Internal bus
ISPR register
xxICn register xxMKn (interrupt mask flag)
INTOV10 INTOV11 INTOV12 INTOV13 INTOV14 INTOV15 INTP100/INTCC100 INTP101/INTCC101 INTP102/INTCC102 INTP103/INTCC103 INTP110/INTCC110 INTP111/INTCC111 INTP112/INTCC112 INTP113/INTCC113 INTP120/INTCC120 INTP121/INTCC121 INTP122/INTCC122 INTP123/INTCC123 INTP130/INTCC130 INTP131/INTCC131 INTP132/INTCC132 INTP133/INTCC133 INTP140/INTCC140 INTP141/INTCC141 INTP142/INTCC142 INTP143/INTCC143 INTP150/INTCC150 INTP151/INTCC151 INTP152/INTCC152 INTP153/INTCC153 INTCM40 INTCM41 INTDMA0 INTDMA1 INTDMA2 INTDMA3 INTCSI0 INTSER0 INTSR0 INTST0 INTCSI1 INTSER1 INTSR1 INTST1 INTCSI2 INTCSI3 INTAD OVIF10 OVIF11 OVIF12 OVIF13 OVIF14 OVIF15 P10IF0 P10IF1 P10IF2 P10IF3 P11IF0 P11IF1 P11IF2 P11IF3 P12IF0 P12IF1 P12IF2 P12IF3 P13IF0 P13IF1 P13IF2 P13IF3 P14IF0 P14IF1 P14IF2 P14IF3 P15IF0 P15IF1 P15IF2 P15IF3 CMIF40 CMIF41 DMAIF0 DMAIF1 DMAIF2 DMAIF3 CSIF0 SEIF0 SRIF0 STIF0 CSIF1 SEIF1 SRIF1 STIF1 CSIF2 CSIF3 ADIF
Handler address generator
3210 3210 3210 3210 3210 3210 3210 3210 3210 3210 3210 3210 Selector Selector Selector Selector Selector Selector 321032103210321032103210
CPU
INTP100 INTP101 INTP102 INTP103
Note
INTM1 (edge detection)
PSW
xxPRn0 to xxPRn3 (interrupt priority order specification bit)
INTP110 INTP111 INTP112 INTP113
ID
Note
INTM2 (edge detection)
Interrupt request Interrupt request acknowledge HALT mode release signal
RPU
INTP120 INTP121 INTP122 INTP123
Note
INTM3 (edge detection)
INTP130 INTP131 INTP132 INTP133
Note
INTM4 (edge detection)
INTP140 INTP141 INTP142 INTP143
Note
INTM5 (edge detection)
INTP150 INTP151 INTP152 INTP153
Note
INTM6 (edge detection)
DMAC CSI0 UART0 SIO CSI1 UART1 CSI2 CSI3 A/D converter NMI
Note Noise elimination Remark xx: OV, CM, P10 to P15, DMA, CS, SE, SR, ST, AD n: None, or 10 to 15, 40, 41, 0 to 3
Preliminary Data Sheet U13995EJ1V0DS00
29
PD703100-33, 703100-40, 703101-33, 703102-33
Table 8-1. List of Interrupts (1/3)
Interrupt/Exception Source Type Category Name Reset Interrupt RESSET Default Control Register - Generation Source RESET input Generating Unit Pin - Priority
Exception Code 0000H
Handler Address
Restore PC
00000000H
Undefined
Nonmaskable Software exception Exception trap Maskable
Interrupt
NMI
-
NMI input
Pin
-
0010H
00000010H
nextPC
Exception Exception Exception
TRAP0n
Note
- - -
TRAP instruction TRAP instruction Illegal instruction code
- - -
- - -
004n 005n
Note
H H
00000040H 00000050H 00000060H
nextPC nextPC nextPC
TRAP1n ILGOP
Note
Note
0060H
Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt
INTOV10 INTOV11 INTOV12 INTOV13 INTOV14 INTOV15 INTP100/ INTCC100
OVIC10 OVIC11 OVIC12 OVIC13 OVIC14 OVIC15 P10IC0
Timer 10 overflow Timer 11 overflow Timer 12 overflow Timer 13 overflow Timer 14 overflow Timer 15 overflow Match between INTP100 and CC100
RPU RPU RPU RPU RPU RPU Pin/RPU
0 1 2 3 4 5 6
0080H 0090H 00A0H 00B0H 00C0H 00D0H 0100H
00000080H 00000090H 000000A0H 000000B0H 000000C0H 000000D0H 00000100H
nextPC nextPC nextPC nextPC nextPC nextPC nextPC
Interrupt
INTP101/ INTCC101
P10IC1
Match between INTP101 and CC101
Pin/RPU
7
0110H
00000110H
nextPC
Interrupt
INTP102/ INTCC102
P10IC2
Match between INTP102 and CC102
Pin/RPU
8
0120H
00000120H
nextPC
Interrupt
INTP103/ INTCC103
P10IC3
Match between INTP103 and CC103
Pin/RPU
9
0130H
00000130H
nextPC
Interrupt
INTP110/ INTCC110
P11IC0
Match between INTP110 and CC110
Pin/RPU
10
0140H
00000140H
nextPC
Interrupt
INTP111/ INTCC111
P11IC1
Match between INTP111 and CC111
Pin/RPU
11
0150H
00000150H
nextPC
Interrupt
INTP112/ INTCC112
P11IC2
Match between INTP112 and CC112
Pin/RPU
12
0160H
00000160H
nextPC
Interrupt
INTP113/ INTCC113
P11IC3
Match between INTP113 and CC113
Pin/RPU
13
0170H
00000170H
nextPC
Interrupt
INTP120/ INTCC120
P12IC0
Match between INTP120 and CC120
Pin/RPU
14
0180H
00000180H
nextPC
Interrupt
INTP121/ INTCC121
P12IC1
Match between INTP121 and CC121
Pin/RPU
15
0190H
00000190H
nextPC
Interrupt
INTP122/ INTCC122
P12IC2
Match between INTP122 and CC122
Pin/RPU
16
01A0H
000001A0H
nextPC
Note n = 0 to FH
30
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Table 8-1. List of Interrupts (2/3)
Interrupt/Exception Source Type Category Name Maskable Interrupt INTP123/ INTCC123 Interrupt INTP130/ INTCC130 Interrupt INTP131/ INTCC131 Interrupt INTP132/ INTCC132 Interrupt INTP133/ INTCC133 Interrupt INTP140/ INTCC140 Interrupt INTP141/ INTCC141 Interrupt INTP142/ INTCC142 Interrupt INTP143/ INTCC143 Interrupt INTP150/ INTCC150 Interrupt INTP151/ INTCC151 Interrupt INTP152/ INTCC152 Interrupt INTP153/ INTC153 Interrupt Interrupt Interrupt INTCM40 INTCM41 INTDMA0 CMIC40 CMIC41 DMAIC0 P15IC3 P15IC2 P15IC1 P15IC0 P14IC3 P14IC2 P14IC1 P14IC0 P13IC3 P13IC2 P13IC1 P13IC0 Default Control Register P12IC3 Generation Source Match between INTP123 and CC123 Match between INTP130 and CC130 Match between INTP131 and CC131 Match between INTP132 and CC132 Match between INTP133 and CC133 Match between INTP140 and CC140 Match between INTP141 and CC141 Match between INTP142 and CC142 Match between INTP143 and CC143 Match between INTP150 and CC150 Match between INTP151 and CC151 Match between INTP152 and CC152 Match between INTP153 and CC153 CM40 match signal CM41 match signal DMA channel 0 transfer completion Interrupt INTDMA1 DMAIC1 DMA channel 1 transfer completion Interrupt INTDMA2 DMAIC2 DMA channel 2 transfer completion Interrupt INTDMA3 DMAIC3 DMA channel 3 transfer completion Interrupt INTCSI0 CSIC0 CSI0 send/receive completion Interrupt INTSER0 SEIC0 UART0 receive error SIO 37 0310H 000000310H nextPC SIO 36 0300H 000000300H nextPC DMAC 35 02D0H 000002D0H nextPC DMAC 34 02C0H 000002C0H nextPC DMAC 33 02B0H 000002B0H nextPC RPU RPU DMAC 30 31 32 0280H 0290H 02A0H 00000280H 00000290H 000002A0H nextPC nextPC nextPC Pin/RPU 29 0270H 00000270H nextPC Pin/RPU 28 0260H 00000260H nextPC Pin/RPU 27 0250H 00000250H nextPC Pin/RPU 26 0240H 00000240H nextPC Pin/RPU 25 0230H 00000230H nextPC Pin/RPU 24 0220H 00000220H nextPC Pin/RPU 23 0210H 00000210H nextPC Pin/RPU 22 0200H 00000200H nextPC Pin/RPU 21 01F0H 000001F0H nextPC Pin/RPU 20 01E0H 000001E0H nextPC Pin/RPU 19 01D0H 000001D0H nextPC Pin/RPU 18 01C0H 000001C0H nextPC Generating Unit Pin/RPU 17 Priority
Exception Code 01B0H
Handler Address
Restore PC
000001B0H
nextPC
Note n = 0 to FH
Preliminary Data Sheet U13995EJ1V0DS00
31
PD703100-33, 703100-40, 703101-33, 703102-33
Table 8-1. List of Interrupts (3/3)
Interrupt/Exception Source Type Category Name Maskable Interrupt INTSR0 Default Control Register SRIC0 Generation Source UART0 receive completion Interrupt INTST0 STIC0 UART0 send completion Interrupt INTCSI1 CSIC1 CSI1 send/receive completion Interrupt Interrupt INTSER1 INTSR1 SEIC1 SRIC1 UART1 receive error UART1 receive completion Interrupt INTST1 STIC1 UART1 send completion Interrupt INTCSI2 CSIC2 CSI2 send/receive completion Interrupt INTCSI3 CSIC3 CSI3 send/receive completion Interrupt INTAD ADIC A/D conversion completion ADC 46 0400H 00000400H nextPC SIO 45 03C0H 000003C0H nextPC SIO 44 0380H 00000380H nextPC SIO 43 0370H 00000370H nextPC SIO SIO 41 42 0350H 0360H 00000350H 00000360H nextPC nextPC SIO 40 0340H 00000340H nextPC SIO 39 0330H 00000330H nextPC Generating Unit SIO 38 Priority
Exception Code 0320H
Handler Address
Restore PC
00000320H
nextPC
Remarks 1. Default priority: Priority that takes precedence when two or more maskable interrupt requests having the same priority level are generated at the same time. The highest priority is 0. Restore PC: The PC value that is saved in EIPC or FEPC when the interrupt or exception processing is started. However, the restore PC value that is saved when an interrupt is acknowledged during the execution of a division instruction (DIV, DIVH, DIVU, or DIVHU), is the PC value of the current instruction (DIV, DIVH, DIVU, or DIVHU). 2. The execution address of the illegal instruction when an illegal opcode exception occurs is obtained according to the calculation "restore PC - 4."
32
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
9. CLOCK GENERATION FUNCTIONS
{ Multiplier function using a PLL (Phase locked loop) synthesizer { Clock sources * * * * * * Oscillation by connecting an oscillator: fXX = /5 External clock: fXX = 2 x or /5 HALT mode IDLE mode Software STOP mode Clock output inhibit mode
{ Power saving modes
{ Internal system clock output function Figure 9-1. Block Diagram of Clock Generation Function
Clock generator (CG)
X1 (fXX) X2 CKSEL
CPU, on-chip peripheral I/O CLKOUT Time base counter (TBC)
Remark : internal system clock frequency FXX: external oscillator or external clock frequency
Preliminary Data Sheet U13995EJ1V0DS00
33
PD703100-33, 703100-40, 703101-33, 703102-33
10. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT)
{ Measures the pulse interval and frequency, and outputs a programmable pulse * * * * * * * * * * * * 16-bit measurements are possible Can generate a variety of pulse patterns (interval pulse, one-shot pulse) 16-bit timer/event counter Count clock sources: 2 types (division of internal system clock, and external pulse input) Capture/compare common registers: 24 Count clear pins: TCLR10 to TCLR15 Interrupt sources: 30 types External pulse outputs: 12 16-bit interval timer Count clock can select division for internal system clock Compare registers: 2 Interrupt sources: 2
{ Timer 1
{ Timer 4
34
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 10-1. Block Diagram of Timer 1 (16-bit Timer/Event Counter)
Internal system clock ( )
TM10
TCLR10 PRM 101 TI10 1/2 1/4 Selector
Edge detection PRS100, ETI10 PRS101
Note 2
Selector
Edge detection m 1/4 1/8 1/16
Clear and count control Clear and start TM10 (16 bits)
OVF10 INTOV10 ALV101 ALV100
Selector
Note 1
INTP100 INTP101 INTP102 INTP103 Noise elimination Edge detection (INTM1)
CC100 CC101 CC102 CC103
S Q RNote 3 Q S Q RNote 3 Q Selector
Selector
TO100 TO101
IMS100 IMS101 IMS102 IMS103 Selector Selector Selector Selector TCLR11 TI11 INTP110 INTP111 INTP112 INTP113 INTP100/INTCC100 INTP101/INTCC101 INTP102/INTCC102 INTP103/INTCC103
TM11
INTOV11 TO110 TO111 INTP110/INTCC110 INTP111/INTCC111 INTP112/INTCC112 INTP113/INTCC113
TCLR15 TI15 INTP150 INTP151 INTP152 INTP153
***
TM15
INTOV15 TO150 TO151 INTP150/INTCC150 INTP151/INTCC151 INTP152/INTCC152 INTP153/INTCC153
Notes 1. Internal count clock 2. External count clock 3. Reset priority
Preliminary Data Sheet U13995EJ1V0DS00
35
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 10-2. Block Diagram of Timer 4 (16-bit Interval Timer)
Internal system clock ( )
TM40
PRM400, PRM401
PRS400
Selector
1/4 1/8
m
1/32
Selector
1/2
1/16
Internal count clock
TM40 (16 bits) Clear and start CM40 INTCM40
TM41 INTCM41
36
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
11. SERIAL INTERFACE FUNCTION
The serial interface function provides two 6-channel serial interfaces. Up to four channels can be used at the same time. (1) Asynchronous serial interface (UART0 and UART1): 2 channels (2) Clocked serial interface (CSI0 to CSI3): 4 channels Caution UART0 and CSI0 share a pin, as do UART1 and CSI1. One or the other of each pair can be selected via a register (ASIM00, ASIM10).
11.1 Asynchronous Serial Interfaces 0, 1 (UART0, UART1)
{ Transfer rate 150 bps to 76800 bps (using the dedicated baud rate generator when the internal system clock is 33 MHz) Maximum 4.125 Mbps (using the /2 clock when the internal system clock is 33 MHz) { Full duplex communications On-chip receive buffer (RXBn) { 2-pin configuration TXDn : Transmit data output pin RXDn: Receive data input pin { Receive error detection functions * * * * * * Parity error Framing error Overrun error Receive error interrupt (INTSERn) Receive completion interrupt (INTSRn) Transmission completion interrupt (INTSTn)
{ Interrupt sources: 3 types
{ The character length of transmission/reception data is specified by the ASIMn0 and ASIMn1 registers. { Character length 7, 8 bits 9 bits (when adding an expansion bit) { Parity function: odd, even, 0, none { Transmission stop bit: 1, 2 bits { On-chip dedicated baud rate generator { Serial clock (SCKn) output function Remark n = 0, 1
Preliminary Data Sheet U13995EJ1V0DS00
37
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 11-1. Block Diagram of Asynchronous Serial Interfaces 0, 1 (UART0, UART1)
UART0 RXB0/RXB0L RXD0 Receive shift register Receive buffer TXS0/TXS0L Transmit shift register Receive control parity check SCLS01, SCLS00 SCK0 1/16 1/16 1/2
Selector
RXE0
TXD0
Transmit control parity addition
INTST0 INTSER0 INTSR0 Internal system clock ( )
BRG0
RXD1 TXD1 SCK1 UART1
INTST1 INTSER1 INTSR1
BRG1
11.2 Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3)
{ High-speed transfer Maximum 10 Mbps (when the internal system clock is operating at 40 MHz) ... PD703100-40 Maximum 8.25 Mbps (when the internal system clock is operating at 33 MHz) ... PD703100-33, PD703101-33,
PD703102-33
{ Half-duplex communications { Character length: 8 bits { Can switch between MSB first or LSB first for data { Either external serial clock input or internal serial clock output can be selected { 3-wire type SOn: SIn: Serial data output Serial data input
SCKn: Serial clock input/output { Interrupt source: 1 type * Transmission/reception completion interrupt (INTCSIn)
Remark n = 0 to 3
38
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 11-2. Block Diagram of Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3)
CSI0 Internal system clock ( ) CRXE0 SI0 Serial I/O shift register (SIO0) SO latch D Q CLS00, CLS01 1/2
Selector
CTXE0 SO0
SCK0
Serial clock control circuit
1/4 BRG0
Serial clock counter
Interrupt control circuit
INTCSI0
SO1 SI1 SCK1 CSI1
1/2 1/4 BRG1 INTCSI1
SO2 SI2 SCK2 CSI2
1/2 1/4 BRG2 INTCSI2
SO3 SI3 SCK3 CSI3
1/2 1/4
INTCSI3
Preliminary Data Sheet U13995EJ1V0DS00
39
PD703100-33, 703100-40, 703101-33, 703102-33
11.3 Dedicated Baud Rate Generators 0 to 2 (BRG0 to BRG2)
{ Serial clock can be selected via either dedicated baud rate generator output or internal system clock () { Identical baud rates during transmission and reception Figure 11-3. Block Diagram of Dedicated Baud Rate Generators 0 to 2 (BRG0 to BRG2)
BRG0
BRGC0 CSI0 UART0 Clear TMBRG0 Prescaler 1/2 Match BRCE0 BPR00 to BPR02 Internal system clock ( )
CSI1 BRG1 UART1
CSI2 BRG2 CSI3
40
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
12. A/D CONVERTER
{ Analog input: 8 channels { On-chip 10-bit A/D converter { On-chip A/D conversion result registers (ADCR0 to ADCR7) 10 bits x 8 { A/D conversion trigger modes A/D trigger mode Timer trigger mode External trigger mode { Successive approximation method Figure 12-1. A/D Converter Block Diagram
Series resistor string ANI0 ANI1
Input circuit
Sample & hold circuit
Tap selector
R/2 R
AVREF
ANI2 ANI3 ANI4 ANI5 ANI6 ANI7
R/2
AVSS AVDD
Voltage comparator 9 SAR (10) 0 10
10 INTAD INTCC110 INTCC111 INTCC112 INTCC113 ADTRG Noise Edge elimination detection 9 ADCR0 Controller ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 7 ADM0 (8) 0 7 ADM1 (8) 0 ADCR6 ADCR7 10 0
8
8
Internal bus
Preliminary Data Sheet U13995EJ1V0DS00
41
PD703100-33, 703100-40, 703101-33, 703102-33
13. PORT FUNCTIONS
{ Number of ports Dedicated input ports: 9 Input/output ports : 114 { Shares pins with other peripheral function I/O { Input and output can be specified in 1-bit units The block diagrams of the various ports are divided into 16 block types identified by A to P as shown in Table 131. Figures 13-1 to 13-16 show the block diagrams of each type. Table 13-1. List of Port Block Types
Port Name Port 0 Pin Name P00 to P07 Port Function 8-bit input/output Function in Control Mode Input/output of real-time pulse unit (RPU), external interrupt input, DMA controller (DMAC) input Input/output of real-time pulse unit (RPU), external interrupt input, DMA controller (DMAC) output NMI input, serial interface (UART0/CSI0, UART1/CSI1) input/output Input/output of real-time pulse unit (RPU), external interrupt input, serial interface (CSI2) input/output External data bus (D0 to D7) External data bus (D8 to D15) External address bus (A16 to A23) A/D converter (ADC) analog input External bus interface control signal output External bus interface control signal input/output Input/output of real-time pulse unit (RPU), external interrupt input, DMA controller (DMAC) output Input/output of real-time pulse unit (RPU), external interrupt input, serial interface (CSI3) input/output Input/output of real-time pulse unit (RPU), external interrupt input, A/D converter (ADC) external trigger input External address bus (A0 to A7) External address bus (A8 to A15) Refresh request signal output, wait insertion signal input, internal system clock output Block Type A, B, M
Port 1
P10 to P17
8-bit input/output
A, B, K
Port 2
P20 to P27
1-bit input, 7-bit input/output 8-bit input/output
A, C, D, I, J
Port 3
P30 to P37
A, B, K, M, N E E F G O, P H, O A, B, K
Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10
P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P107 P110 to P117 P120 to P127 PA0 to PA7 PB0 to PB7 PX5 to PX7
8-bit input/output 8-bit input/output 8-bit input/output 8-bit input/output 8-bit input/output 8-bit input/output 8-bit input/output
Port 11
8-bit input/output
A, B, K, M, N A, B
Port 12
8-bit input/output
Port A Port B Port X
8-bit input/output 8-bit input/output 3-bit input/output
F F A, L
42
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-1. Block Diagram of Type A
WRPMC PMCmn WRPM PMmn
Internal bus
Selector
WRPORT
Output signal in control mode Pmn
Pmn
Selector
RDIN
Address
Remark m: port number n : bit number Figure 13-2. Block Diagram of Type B
WRPMC PMCmn WRPM PMmn
Internal bus
WRPORT Pmn Pmn
Selector
Address RDIN Input signal in control mode Noise elimination Edge detection
Remark m: port number n : bit number
Selector
Selector
Preliminary Data Sheet U13995EJ1V0DS00
43
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-3. Block Diagram of Type C
WRPMC PMCmn WRPM PMmn
Internal bus
SCKx output enable signal
Selector
WRPORT
Output signal in control mode Pmn
Pmn
Selector
Address RDIN Input signal in control mode
Remark mn: 24, 27 x : 0 (when mn = 24), 1 (when mn = 27) Figure 13-4. Block Diagram of Type D
WRPMC PMCmn WRPM PMmn
Internal bus
WRPORT Pmn Pmn
Selector
Address RDIN Input signal in control mode
Remark m: port number n : bit number
44
Preliminary Data Sheet U13995EJ1V0DS00
Selector
Selector
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-5. Block Diagram of Type E
MODE0 to MODE3 MM0 to MM3
I/O control circuit WRPM PMmn
Internal bus
Selector
WRPORT
Output signal in control mode Pmn
Pmn
Selector
Address RDIN Input signal in control mode
Remark m: port number n : bit number Figure 13-6. Block Diagram of Type F
MODE0 to MODE3 MM0 to MM3
I/O control circuit WRPM PMmn
Internal bus
Selector
WRPORT
Output signal in control mode Pmn
Selector
Pmn
Selector
Address RDIN
Remark m: port number n : bit number
Selector
Preliminary Data Sheet U13995EJ1V0DS00
45
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-7. Block Diagram of Type G
Internal bus
P7n
RDIN Input signal in control mode Sample & hold circuit
ANIn
Remark n = 0 to 7 Figure 13-8. Block Diagram of Type H
MODE0 to MODE3 MM0 to MM3
I/O control circuit WRPM PMmn
Internal bus
WRPORT Pmn P97
Selector
Address RDIN Input signal in control mode
46
Preliminary Data Sheet U13995EJ1V0DS00
Selector
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-9. Block Diagram of Type I
Internal bus
Selector
1 Noise elimination P20
RDIN
Address
NMI
Edge detection
Figure 13-10. Block Diagram of Type J
WRPM PMmn
Internal bus
WRPORT Pmn Pmn
Selector
RDIN
Address
Remark m: port number n : bit number
Selector
Preliminary Data Sheet U13995EJ1V0DS00
47
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-11. Block Diagram of Type K
WRPCS PCSmn WRPMC PMCmn WRPM
Internal bus
PMmn
Selector
WRPORT
Output signal in control mode Pmn
Pmn
Selector
Address RDIN Input signal in control mode Noise elimination Edge detection
Remark m: port number n : bit number
48
Preliminary Data Sheet U13995EJ1V0DS00
Selector
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-12. Block Diagram of Type L
WRPMC PMCmn WRPM PMmn
Internal bus
WRPORT Pmn Pmn
Selector
Address RDIN Input signal in control mode
Remark m: port number n : bit number
Selector
Preliminary Data Sheet U13995EJ1V0DS00
49
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-13. Block Diagram of Type M
WRPCS PCSmnNote WRPMC PMCmn WRPM
Internal bus
PMmn WRPORT Pmn
Selector
Pmn
Address RDIN INTP100 to INTP103, INTP132, INTP142 DMARQ0 to DMARQ3, SI2, SI3 Noise elimination Edge detection
Note When mn = 36:
PCS35
When mn = 116: PCS115 Remark mn: 04 to 07, 36, 116
50
Preliminary Data Sheet U13995EJ1V0DS00
Selector
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-14. Block Diagram of Type N
WRPCS PCSm5 WRPMC PMCmn WRPM
Internal bus
SCKx output enable signal
PMmn
Selector
WRPORT
Output signal in control mode Pmn
Pmn
Selector
Address
RDIN INTP133, INTP143 SCK2, SCK3 Noise elimination Edge detection
Remark mn: 37, 117 x: 2 (when mn = 37), 3 (when mn = 117)
Selector
Preliminary Data Sheet U13995EJ1V0DS00
51
PD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-15. Block Diagram of Type O
WRPMC PMCmn I/O control circuit WRPM PMmn
Internal bus
MODE0 to MODE3
MM0 to MM3
Selector
WRPORT
Output signal in control mode Pmn
Pmn
Selector
Address RDIN
Remark m: port number n : bit number Figure 13-16. Block Diagram of Type P
WRPCS PCSmn WRPMC PMCmn WRPM
Internal bus
MODE0 to MODE3
Selector
MM0 to MM3
I/O control circuit
PMmn
Selector
WRPORT
Output signal in control mode Pmn
Selector
Pmn
Selector
Address RDIN
Remark m: port number n : bit number
52
Preliminary Data Sheet U13995EJ1V0DS00
Selector
PD703100-33, 703100-40, 703101-33, 703102-33
14. RESET FUNCTION
When low-level signal is input to the RESET pin, a system reset is performed and the various on-chip hardware devices are initialized. When the RESET input changes from low to high, the reset state is canceled and the CPU begins program execution. (the contents of the various registers should be initialized within the program as necessary.) An on-chip noise elimination circuit, which uses analog delay ( = 60 ns) to eliminate noise, is provided for the RESET pin.
Preliminary Data Sheet U13995EJ1V0DS00
53
PD703100-33, 703100-40, 703101-33, 703102-33
15. INSTRUCTION SET
Table 15-1. Symbols Used to Describe Operands
Symbol reg1 reg2 reg3 Description General registers (r0 to r31): used as source registers General registers (r0 to r31): used mainly as destination registers General registers (r0 to r31): used mainly to store the remainders of division results and the higher 3 bits of multiplication results x-bit immediate x-bit displacement System register number 3-bit data for specifying the bit number Element pointer (r30) 4-bit data indicating the condition code 5-bit data used for specifying the trap vector (00H to 1FH) List of x registers
immx dispx regID bit#3 ep cccc vector listx
Table 15-2. Symbols Used to Describe Opcodes
Symbol R r w d i cccc bbb L 1-bit data of code specifying reg1 or regID 1-bit data of code specifying reg2 1-bit data of code specifying reg3 1-bit displacement data 1-bit immediate data 4-bit data indicating condition code 3-bit data for specifying bit number 1-bit data specifying register list Description
54
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Table 15-3. Symbols Used in Operation
Symbol GR [ ] SR [ ] zero-extend (n) sign-extend (n) load-memory (a, b) store-memory (a, b, c) load-memory-bit (a, b) store-memory-bit (a, b, c) saturated (n) Input for General register System register Extend n with zeros until word length Extend n with signs until word length Read data of size b from address a Write data b of address a by size c Read bit b of address a Write c to bit b of address a Execute saturation processing of n (n is a two's complement) If, as a result of the calculation, n 7FFFFFFFH, let it be 7FFFFFFFH. n 80000000H, let it be 80000000H Reflect the result in a flag Byte (8 bits) Half word (16 bits) Word (32 bits) Add Subtract Bit concatenation Multiply Divide Remainder of division result Logical AND Logical OR Exclusive OR Logical NOT Logical shift left Logical shift right Arithmetic shift right Description
result Byte Half-word Word + - || x / % AND OR XOR NOT logically shift left by logically shift right by arithmetically shift right by
Table 15-4. Symbols Used for Execution Clock
Symbol i : issue r : repeat l : latency Description When executing another instruction immediately after executing an instruction When repeating the same instruction immediately after executing the instruction When referring to instruction execution results in the next instruction
Preliminary Data Sheet U13995EJ1V0DS00
55
PD703100-33, 703100-40, 703101-33, 703102-33
Table 15-5. Symbols Used in Flag Operations
Identifier (Blank) 0 x R No change Clear to 0 Set or cleared according to the results Previously saved values are restored Description
Table 15-6. Condition Codes
Condition Name (cond) V NV C/L Condition Code (cccc) 0000 1000 0001 OV = 1 OV = 0 CY = 1
Condition Formula Overflow No overflow
Description
Carry Lower (Less than) No carry Not lower (Greater than or equal) Zero Equal Not zero Not equal Not higher (Less than or equal) Higher (Greater than) Negative Positive - Always (unconditional) Saturated Less than signed Greater than or equal signed Less than or equal signed Greater than signed
NC/NL
1001
CY = 0
Z/E
0010
Z=1
NZ/NE
1010
Z=0
NH H N P T SA LT GE LE GT
0011 1011 0100 1100 0101 1101 0110 1110 0111 1111
(CY or Z) = 1 (CY or Z) = 0 S=1 S=0
SAT = 1 (S xor OV) = 1 (S xor OV) = 0 ((S xor OV) or Z) = 1 ((S xor OV) or Z) = 0
56
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Instruction Set (1/7)
Execution Mnemonic Operand Opcode Operation i ADD reg1,reg2 imm5,reg2 ADDI imm16,reg1,reg2 rr r r r 0 0 1 1 1 0 R R R R R GR[reg2]GR[reg2]+GR[reg1] rr r r r 0 1 0 0 1 0 i i i i i GR[reg2]GR[reg2]+sign-extend(imm5) r r r r r 1 1 0 0 0 0 r r r r r GR[reg2]GR[reg1]+sign-extend(imm16) i i ii i i i i i i i i i i i i AND ANDI reg1,reg2 imm16,reg1,reg2 rr r r r 0 0 1 0 1 0 R R R R R GR[reg2]GR[reg2]AND GR[reg1] rr r r r 1 1 0 1 1 0 R R R R R GR[reg2]GR[reg1]AND zeroi i i i i i i i i i i i i i i i extend(imm16) Bcond disp9 dd d d d 1 0 1 1 d d d c c c c if conditions are satisfied Note 1 then PC PC+signextend(disp9) When conditions are satisfied When conditions are not satisfied BSH reg2,reg3 rr r r r 1 1 1 1 1 1 0 0 0 0 0 GR[reg3]GR[reg2] (23 : 16) II GR[reg2] ww w w w 0 1 1 0 1 0 0 0 0 1 0 (31 : 24) II GR[reg2] (7 : 0) II GR[reg2] (15 : 8) BSW reg2,reg3 rr r r r 1 1 1 1 1 1 0 0 0 0 0 GR[reg3]GR[reg2] (7 : 0) II GR[reg2] (15 : 8) II ww w w w 0 1 1 0 1 0 0 0 0 0 0 GR[reg2] (23 : 16) II GR[reg2] (31 : 24) CALLT imm6 0 0 0 0 0 0 1 0 0 0 i i i i i i CTPCPC+2(return PC) CTPSWPSW adrCTBP+zero-extend(imm6 logically shift left by 1) PCCTBP+zero-extend(Loadmemory(adr, Half-word)) CLR1 bit#3, disp 16[reg1] 1 0 b b b 1 1 1 1 1 0 R R R R R adrGR[reg1]+sign-extend(disp16) dd d d d d d d d d d d d d d d Z flagsNot(Load-memory-bit(adr,bit#3)) Store-memory-bit (adr,bit#3,0) reg2,[reg1] rr r r r 1 1 1 1 1 1 R R R R R adrGR[reg1] 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 Z flagsNot(Load-memory-bit(adr,reg2)) Store-memory-bit (adr,reg2,0) CMOV cccc,imm5,reg2, reg3 rr r r r 1 1 1 1 1 1 i i i i i if condition are satisfied then ww w w w 0 1 1 0 0 0 c c c c 0 GR[reg3]sign-extended(imm5) else GR[reg3]GR[reg2] cccc,reg1,reg2, reg3 rr r r r 1 1 1 1 1 1 R R R R R if conditions are satisfied ww w w w 0 1 1 0 0 1 c c c c 0 then GR[reg3]GR[reg1] else GR[reg3]GR[reg2] CMP reg1,reg2 imm5,reg2 CTRET rr r r r 0 0 1 1 1 1 R R R R R resultGR[reg2]-GR[reg1] rr r r r 0 1 0 0 1 1 i i i i i resultGR[reg2]-sign-extend(imm5) 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PCCTPC 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 PSWCTPSW DI 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID1 00 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 1 1 1 1 3 1 1 3 1 1 3 x x R x x R x x R x x R R 1 1 1 1 1 1 3 3 3 x 3 3 3 x 4 4 4 1 1 1 x 0 x x 1 1 1 x 0 x x 1 1 1 2 2 2 1 1 1 1 1 1 0 0 x 0 x x 1 1 1 Clock r 1 1 1 l 1 1 1 CY x x x OV x x x Flags S x x x Z x x x SAT
Note 2 Note 2 Note 2
Note 3 Note 3 Note 3
Note 3 Note 3 Note 3
Preliminary Data Sheet U13995EJ1V0DS00
57
PD703100-33, 703100-40, 703101-33, 703102-33
(2/7)
Execution Mnemonic Operand Opcode Operation i DISPOSE imm5,list12 Clock r l CY OV Flags S Z SAT
0 0 0 0 0 1 1 0 0 1 i i i i i L spsp+zero-extend(imm5 logically shift left N+1 N+1 N+1 LL L L L L L L L L L 0 0 0 0 0 by 2) GR[reg in list12]Load-memory(sp,Word) spsp+4 repeat 2 steps above untill all regs in list12 is loaded Note 4 Note 4 Note 4
imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i L spsp+zero-extend(imm5 logically shif left LL L L L L L L L L L R R R R R by 2) Note 5 GR[reg in list12]Load-memory(sp,Word) spsp+4 repeat 2 steps above until all regs in list 12 is loaded PCGR[reg1] DIV reg1,reg2,reg3 rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]GR[reg2]/GR[reg1] w w w w w 0 1 0 1 1 0 0 0 0 0 0 GR[reg3]GR[reg2]%GR[reg1] DIVH reg1,reg2 reg1,reg2,reg3 r r r r r 0 0 0 0 1 0 R R R R R GR[reg2]GR[reg2]/GR[reg1] Note 6 r r r r r 1 1 1 1 1 1 R R R R R GR[reg2]GR[reg2]/GR[reg1]
Note 6
N+3 N+3 N+3 Note 4 Note 4 Note 4
35
35
35
35 35
35 35
35 35
x x
x x
x x
w w w w w 0 1 0 1 0 0 0 0 0 0 0 GR[reg3]GR[reg2]%GR[reg1] DIVHU reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 R R R R R GR[reg2]GR[reg2]/GR[reg1] Note 6 w w w w w 0 1 0 1 0 0 0 0 0 1 0 GR[reg3]GR[reg2]%GR[reg1] DIVU reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 R R R R R GR[reg2]GR[reg2]/GR[reg1] w w w w w 0 1 0 1 1 0 0 0 0 1 0 GR[reg3]GR[reg2]%GR[reg1] EI 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID0 00 0 0 0 0 0 1 0 1 1 0 0 0 0 0 HALT 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 Stop 00 0 0 0 0 0 1 0 0 1 0 0 0 0 0 HSW reg2,reg3 rr r r r 1 1 1 1 1 1 0 0 0 0 0 GR[reg3]GR[reg2] (15 : 0) II GR[reg2] w w w w w 0 1 1 0 1 0 0 0 1 00 JARL disp22,reg2 (31: 6) 2 2 2 1 1 1 x 0 x x 1 1 1 1 1 1 34 34 34 x x x 34 34 34 x x x
rr r r r 1 1 1 1 0 d d d d d d GR[reg2]PC+4 dd d d d d d d d d d d d d d 0 PCPC+sign-extend(disp22) Note 7
JMP JR
[reg1] disp22
0 0 0 0 0 0 0 0 0 1 1 R R R R R PCGR[reg1] 0 0 0 0 0 1 1 1 1 0 d d d d d d PCPC+sign-extend(disp22) dd d d d d d d d d d d d d d 0 Note 7
3 2
3 2
3 2
LD.B
disp16[reg1],reg2
rr r r r 1 1 1 0 0 0 R R R R R adrGR[reg1]+signe-extend(disp16) dd d d d d d d d d d d d d d d GR[reg2]sign-extend(Load-memory (adr,Byte))
1
1
n Note 9
58
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(3/7)
Execution Mnemonic Operand Opcode Operation i LD.BU disp16[reg1],reg2 rr r r r 1 1 1 1 0 b R R R R R adrGR[reg1]+sign-extend(disp16) dd d d d d d d d d d d d d d 1 GR[reg2]zero-extend(Load-memory Notes 8, 10 (adr,Byte)) LD.H disp16[reg1],reg2 rr r r r 1 1 1 0 0 1 R R R R R adrGR[reg1]+sign-extend(disp16) dd d d d d d d d d d d d d d 0 GR[reg2]sign-extend(Load-memory Note 8 (adr,Half-word)) LD.HU disp16[reg1],reg2 rr r r r 1 1 1 1 1 1 R R R R R adrGR[reg1]+sign-extend(disp16) dd d d d d d d d d d d d d d 1 GR[reg2]zero-extend(Load-memory Note 8 (adr,Half-word)) LD.W disp16[reg1],reg2 rr r r r 1 1 1 0 0 1 R R R R R adrGR[reg1]+signe-extend(disp16) dd d d d d d d d d d d d d d 1 GR[reg2]Load-memory(adr,Word) LDSR reg2,regID rr r r r 1 1 1 1 1 1 R R R R R SR[regID]GR[reg2] 00 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Note 12 MOV reg1,reg2 imm5,reg2 imm32,reg1 rr r r r 0 0 0 0 0 0 R R R R R GR[reg2]GR[reg1] rr r r r 0 1 0 0 0 0 i i i i i GR[reg2]sign-extend(imm5) 0 0 0 0 0 1 1 0 0 0 1 R R R R R GR[reg1]imm32 ii i i i i i i i i i i i i i i ii i i i i i i i i i i i i i i MOVEA imm16,reg1,reg2 rr r r r 1 1 0 0 0 1 R R R R R GR[reg2]GR[reg1]+ sign-extend(imm16) ii i i i i i i i i i i i i i i MOVHI imm16,reg1,reg2 rr r r r 1 1 0 0 1 0 R R R R R GR[reg2]GR[reg1]+(imm16 II 016) ii i i i i i i i i i i i i i i MUL reg1,reg2,reg3 rr r r r 1 1 1 1 1 1 R R R R R GR[reg3] II GR[reg2]GR[reg2] x GR[reg1] ww w w w 0 1 0 0 0 1 0 0 0 0 0 imm9,reg2,reg3 rr r r r 1 1 1 1 1 1 i i i i i GR[reg3] II GR[reg2]GR[reg2] x signw w w w w 0 1 0 0 1 1 1 1 1 0 0 extend(imm9) Note 13 MULH reg1,reg2 imm5,reg2 MULHI imm16,reg1,reg2 rr r r r 0 0 0 1 1 1 R R R R R GR[reg2]GR[reg2] rr r r r 0 1 0 1 1 1 i i i i i GR[reg2]GR[reg2]
Note 6
Clock r 1 l n Note 11 CY OV
Flags S Z SAT
1
1
1
n Note 9
1
1
n Note 11
1
1
n Note 9
Other than regID=PSW
regID=PSW
1
1
1
x 1 1 2 1 1 2 1 1 2
x
x
x
x
1
1
1
1
1
1
1
2 Note 14
2
1
2 Note 14
2
x GR[reg1]
Note 6
1 1 1
1 1 1
2 2 2
Note 6
x sign-extend (imm5) x imm16
rr r r r 1 1 0 1 1 R R R R R R GR[reg2]GR[reg1] ii i i i i i i i i i i i i i i
Note 6
Preliminary Data Sheet U13995EJ1V0DS00
59
PD703100-33, 703100-40, 703101-33, 703102-33
(4/7)
Execution Mnemonic Operand Opcode Operation i MULU reg1,reg2,reg3 rr r r r 1 1 1 1 1 1 R R R R R GR[reg3] II GR[reg2]GR[reg2] x GR[reg1] w w w w w 0 1 0 0 0 1 0 0 0 10 imm9,reg2,reg3 r r r r r 1 1 1 1 1 1 i i i i i GR[reg3] II GR[reg2]GR[reg2] x zeroww w w w 0 1 0 0 1 1 1 1 1 1 0 extend(imm9) NOP NOT NOT1 reg1,reg2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pass at least one clock cycle doing nothing rr r r r 0 0 0 0 0 1 R R R R R GR[reg2]NOT(GR[reg1]) 1 1 3 1 1 Clock r 2 Note 14 2 Note 14 1 1 3 1 1 3 0 x x x 2 l 2 CY OV Flags S Z SAT
bit#3,disp16[reg1] 0 1 b b b 1 1 1 1 1 0 R R R R R adrGR[reg1]+sign-extend(disp16) dd d d d d d d d d d d d d d d Z flagNot(Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,Z flag) reg2,[reg1] rr r r r 1 1 1 1 1 1 R R R R R adrGR[reg1] 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,Z flag)
Note 3 Note 3 Note 3
3
3
3
x
Note 3 Note 3 Note 3
OR ORI
reg1,reg2 imm16,reg1,reg2
rr r r r 0 0 1 0 0 0 R R R R R GR[reg2]GR[reg2] OR GR[reg1] rr r r r 1 1 0 1 0 0 R R R R R GR[reg2]GR[reg1] OR zeroi i i i i i i i i i i i i i i i extend(imm16)
1 1
1 1
1 1
0 0
x x
x x
PREPARE
list12,imm5
0 0 0 0 0 1 1 1 1 0 i i i i i L Store-memory(sp-4,GR[reg in list12],Word) LL L L L L L L L L L 0 0 0 0 1 spsp-4 repeat 1 step above until all regs in list12 is stored spsp-zero-extend(imm5)
N+1 N+1 N+1 Note 4 Note 4 Note 4
list12,imm5, sp/imm
Note 15
0 0 0 0 0 1 1 1 1 0 i i i i i L Store-memory(sp-4,GR[reg in list12],Word) LL L L L L L L L L L f f 0 1 1 spsp-4 imm16/imm32
N+2 N+2 N+2 Note 4 Note 4 Note 4
repeat 1 step above until all regs in list12 is Note 17 Note 17 Note 17 Note 16 stored spsp-zero-extend(imm5)
RETI
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 if PSW.EP=1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 then PC PSW EIPC EIPSW PC FEPC EIPC
3
3
3
R
R
R
R
R
else if PSW.NP = 1 then PSW FEPSW else PC PSW EIPSW SAR reg1,reg2 rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]GR[reg2]arithmetically shift right 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 by GR[reg1] imm5,reg2 rr r r r 0 1 0 1 0 1 i i i i i GR[reg2]GR[reg2]arithmetically shift right by zero-extend(imm5) SASF cccc,reg2 rr r r r 1 1 1 1 1 0 c c c c c if conditions are satisfied 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 then GR[reg2](GR[reg2] Logically shift left by 1) OR 00000001H else GR[reg2](GR[reg2] Logically shift left by 1) OR 00000000H 1 1 1 1 1 1 x 0 x x 1 1 1 x 0 x x
60
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(5/7)
Execution Mnemonic Operand Opcode Operation i SATADD reg1,reg2 imm5,reg2 rr r r r 0 0 0 1 1 0 R R R R R GR[reg2]saturated(GR[reg2]+GR[reg1]) rr r r r 0 1 0 0 0 1 i i i i i GR[reg2]saturated(GR[reg2]+signextend(imm5) SATSUB SATSUBI reg1,reg2 imm16,reg1,reg2 rr r r r 0 0 0 1 0 1 R R R R R GR[reg2]saturated(GR[reg2]-GR[reg1]) rr r r r 1 1 0 0 1 1 R R R R R GR[reg2]saturated(GR[reg1]-signi i i i i i i i i i i i i i i i extend(imm16) SATSUBR SETF reg1,reg2 cccc,reg2 rr r r r 0 0 0 1 0 0 R R R R R GR[reg2]saturated(GR[reg1]-GR[reg2]) rr r r r 1 1 1 1 1 1 0 c c c c If conditions are satisfied 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 then GR[reg2]00000001H else GR[reg2]00000000H SET1 bit#3,disp16[reg1] 0 0 b b b 1 1 1 1 1 0 R R R R R adrGR[reg1]+sign-extend(disp16) dd d d d d d d d d d d d d d d Z flagNot(Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,1) reg2,[reg1] rr r r r 1 1 1 1 1 1 R R R R R adrGR[reg1] 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,1) SHL reg1,reg2 rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]GR[reg2] logically shift left by 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 GR[reg1] imm5,reg2 rr r r r 0 1 0 1 1 0 i i i i i GR[reg2]GR[reg2] logically shift left by zero-extend(imm5) SHR reg1,reg2 rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]GR[reg2] logically shift right by 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 GR[reg1] imm5,reg2 rr r r r 0 1 0 1 0 0 i i i i i GR[reg2]GR[reg2] logically shift right by zero-extend(imm5) SLD.B disp7[ep],reg2 rr r r r 0 1 1 0 d d d d d d d adrep+zero-extend(disp7) GR[reg2]sign-extend(Loadmemory(adr,Byte)) SLD.BU disp4[ep],reg2 rr r r r 0 0 0 0 1 1 0 d d d d adrep+zero-extend(disp4) GR[reg2]zero-extend(LoadNote 18 SLD.H disp8[ep],reg2 memory(adr,Byte)) rr r r r 1 0 0 0 d d d d d d d adrep+zero-extend(disp8) Note 19 GR[reg2]sign-extend(Loadmemory(adr,Half-word)) SLD.HU disp5[ep],reg2 rr r r r 0 0 0 0 1 1 1 d d d d adrep+zero-extend(disp5) GR[reg2]zero-extend(LoadNotes 18, 20 SLD.W disp8[ep],reg2 memory(adr,Half-word)) rr r r r 1 0 1 0 d d d d d d 0 adrep+zero-extend(disp8) Note 21 SST.B reg2,disp7[ep] GR[reg2]Load-memory(adr,Word)) 1 1 1 1 n Note 9 1 1 1 n Note 9 1 1 n Note 9 1 1 n Note 9 1 1 n Note 9 1 1 1 x 0 x x 1 1 1 x 0 x x 1 1 1 x 0 x x 1 1 1 x 0 x x 3 3 3 x 3 3 3 x 1 1 1 1 1 1 x x x x x 1 1 1 1 1 1 x x x x x x x x x x 1 1 Clock r 1 1 l 1 1 CY x x OV x x Flags S x x Z x x SAT x x
Note 3 Note 3 Note 3
Note 3 Note 3 Note 3
rr r r r 0 1 1 1 d d d d d d d adrep+zero-extend(disp7) Store-memory(adr,GR[reg2],Byte)
Preliminary Data Sheet U13995EJ1V0DS00
61
PD703100-33, 703100-40, 703101-33, 703102-33
(6/7)
Execution Mnemonic Operand Opcode Operation i SST.H reg2,disp8[ep] rr r r r 1 0 0 1 d d d d d d d adrep+zero-extend(disp8) Note 19 Store-memory(adr,GR[reg2],Half-word) SST.W reg2,disp8[ep] rr r r r 1 0 1 0 d d d d d d 1 adrep+zero-extend(disp8) Note 21 Store-memory(adr,GR[reg2],Word) ST.B reg2,disp16[reg1] rr r r r 1 1 1 0 1 0 R R R R R adrGR[reg1]+sign-extend(disp16) dd d d d d d d d d d d d d d d Store-memory(adr,GR[reg2],Byte) ST.H reg2,disp16[reg1] rr r r r 1 1 1 0 1 1 R R R R R adrGR[reg1]+sign-extend(disp16) dd d d d d d d d d d d d d d 0 Store-memory(adr,GR[reg2],Half-word) Note 8 ST.W reg2,disp16[reg1] rr r r r 1 1 1 0 1 1 R R R R R adrGR[reg1]+sign-extend(disp16) dd d d d d d d d d d d d d d 1 Store-memory(adr,GR[reg2],Word) Note 8 STSR regID,reg2 rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]SR[regID] 00 0 0 0 0 0 0 0 1 0 0 0 0 0 0 SUB SUBR SWITCH reg1,reg2 reg1,reg2 reg1 rr r r r 0 0 1 1 0 1 R R R R R GR[reg2]GR[reg2]-GR[reg1] rr r r r 0 0 1 1 0 0 R R R R R GR[reg2]GR[reg1]-GR[reg2] 0 0 0 0 0 0 0 0 0 1 0 R R R R R adr(PC+2)+(GR[reg1] logically shift left by 1) PC(PC+2)+sign-extend((Loadmemory(adr,Hafl-word)) logically shift left by 1) SXB reg1 0 0 0 0 0 0 0 0 1 0 1 R R R R R GR[reg1]sign-extend (GR[reg1] (7 : 0) SXH reg1 0 0 0 0 0 0 0 0 1 1 1 R R R R R GR[reg1]sign-extend (GR[reg1] (15 : 0)) TRAP vector 0 0 0 0 0 1 1 1 1 1 1 i i i i i EIPC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 EIPSW ECR.EICC PSW.EP PSW.ID PC PC+4 (restore PC) PSW Interrupt code 1 1 00000040H (when vector is 00H to 0FH) 00000050H (when vector is 10H to 1FH) TST TST1 reg1,reg2 rr r r r 0 0 1 0 1 1 R R R R R resultGR[reg2] AND GR[reg1] 1 3 1 3 1 3 0 x x x 3 3 3 1 1 1 1 1 1 1 1 5 1 1 5 1 1 5 x x x x x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Clock r 1 l 1 CY OV Flags S Z SAT
bit#3,disp16[reg1] 1 1 b b b 1 1 1 1 1 0 R R R R R adrGR[reg1]+sign-extend(disp16) dd d d d d d d d d d d d d d d Z flagNot(Load-memory-bit(adr,bit#3)) reg2,[reg1] rr r r r 1 1 1 1 1 1 R R R R R adrGR[reg1] 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 Z flagNot(Load-memory-bit(adr,reg2))
Note 3 Note 3 Note 3 3 3 3 x
Note 3 Note 3 Note 3
62
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(7/7)
Execution Mnemonic Operand Opcode Operation i XOR XORI reg1,reg2 imm16,reg1,reg2 rr r r r 0 0 1 0 0 1 R R R R R GR[reg2]GR[reg2] XOR GR[reg1] rr r r r 1 1 0 1 0 1 R R R R R GR[reg2]GR[reg1] XOR zero-extend ii i i i i i i i i i i i i i i ZXB ZXH reg1 reg1 (imm16) 1 1 1 1 1 1 1 1 Clock r 1 1 l 1 1 CY OV 0 0 Flags S x x Z x x SAT
0 0 0 0 0 0 0 0 1 0 0 R R R R R GR[reg1]zero-extend(GR[reg1] (7 : 0)) 0 0 0 0 0 0 0 0 1 1 0 R R R R R GR[reg1]zero-extend(GR[reg1] (15 : 0))
Notes 1. dddddddd: Higher 8 bits of disp9. 2. 3 clocks if the final instruction includes PSW write access. 3. If there is no wait state (3 + the number of read access wait states). 4. N is the total number of list 12 read registers. (according to the number of wait states. Also, if there are no wait states, N is the number of list 12 registers.) 5. RRRRR other than 00000. 6. Only the lower half word data are valid. 7. ddddddddddddddddddddd: Higher 21 bits of disp22. 8. ddddddddddddddd: Higher 15 bits of disp16. 9. According to the number of wait states (1 if there are no wait states). 10. b: bit 0 of disp16. 11. According to the number of wait states (2 if there are no wait states). 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the op code. Therefore, the meaning of the register specification in the mnemonic description and in the opcode differs from other instructions. rrrrr : regID specification RRRRR: reg2 specification 13. 11111: Lower 5 bits of imm9. 1111 : Lower 4 bits of imm9. 14. 1 when r = w (the lower 32 bits of the results are not written in the register) or w = r0 (the higher 32 bits of the results are not written in the register). 15. sp/imm: specified by bits 19 and 20 of the sub opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. If imm=imm32, N + 3 clocks. 18. rrrrr other than 00000. 19. ddddddd: Higher 7 bits of disp8. 20. dddd: Higher 4 bits of disp5. 21. dddddd: Higher 6 bits of disp8.
Preliminary Data Sheet U13995EJ1V0DS00
63
PD703100-33, 703100-40, 703101-33, 703102-33
16. ELECTRICAL SPECIFICATIONS (PRELIMINARY VALUES)
Absolute Maximum Ratings (TA = 25C)
Parameter Power supply voltage Symbol VDD HVDD CVDD CVSS AVDD AVSS Input voltage VI VDD pin HVDD pin, HVDD VDD CVDD pin CVSS pin AVDD pin AVSS pin X1 pin, except MODE3 pin MODE3 pin Clock input voltage Low-level output current VK IOL X1, VDD = 3.0 to 3.6 V 1 pin Total of all pins High-level output current LOH 1 pin Total of all pins Output voltage Analog input voltage VO VIAN HVDD = 5.0 V 10 % P70/ANI0 to P77/ANI7 pins AVDD > HVDD HVDD AVDD TA AVDD > HVDD HVDD AVDD Condition Rating -0.5 to +4.6 -0.5 to +7.0 -0.5 to +4.6 -0.5 to +0.5 -0.5 to HVDD + 0.5 -0.5 to +0.5 -0.5 to HVDD + 0.5 -0.5 to VDD + 0.5 -0.5 to VDD + 1.0 4.0 100 -4.0 -100 -0.5 to HVDD + 0.5 -0.5 to HVDD + 0.5 -0.5 to AVDD + 0.5 -0.5 to HVDD + 0.5 -0.5 to AVDD + 0.5 -40 to +70 -40 to +85 -60 to +150 Unit V V V V V V V V V mA mA mA mA V V V V V C C C
A/D converter reference input voltage Operating ambient temperature
AVREF
PD703100-40 PD703100-33, 703101-33, 703102-33
Storage temperature
Tstg
Caution
1. Do not make direct connections of the output (or input/output) pins of the IC product with each other, and also avoid direct connections to VDD, VCC, or GND. However, the open drain pins or the open collector pins can be directly connected with each other. A direct connection can also be made for an external circuit designed with timing specifications that prevent conflicting output from pins subject to high-impedance state. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions shown below for DC characteristics and AC characteristics are within the range for normal operation and quality assurance.
64
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Capacitance (TA = 25C, VDD = HVDD = CVDD = VSS = 0 V)
Parameter Input capacitance Input/output capacitance Output capacitance Symbol CI CIO CO Condition fc = 1 MHz Unmeasured pins returned to 0 V. MIN. TYP. MAX.
15 15 15
Unit pF pF pF
Operating Conditions
Operation Mode Direct mode Operating Ambient Temperature (TA) -40 to +70C -40 to +85C -40 to +70C -40 to +85C Power Supply Voltage (VDD, HVDD) VDD = 3.0 to 3.6 V, HVDD = 5.0 V 10%
Internal Operating Clock Frequency ()
PD703100-40 PD703100-33, 703101-33, 703102-33
2 to 40 MHz 2 to 33 MHz 20 to 40 MHz 20 to 33 MHz
PLL mode
PD703100-40 PD703100-33, 703101-33, 703102-33
Recommended Oscillation Circuits
(a) Ceramic resonator or crystal resonator connection (TA = -40 to +70C ... PD703100-40, TA = -40 to +85C ... PD703100-33, PD703101-33, PD703102-33)
X1 X2
C1
C2
Cautions
1. Connect the oscillation circuit as closely to the X1 and X2 pins as possible. 2. Do not wire any other signal lines in the area indicated by the broken line. 3. Throughly evaluate the matching between the PD703100-33, PD703100-40, PD703101-33, and PD703102-33 and the oscillators.
(b) External clock input (TA = -40 to +70C ... PD703100-40, TA = -40 to +85C ... PD703100-33, PD703101 33, PD703102-33)
X1 X2 Open
External clock
Caution Input CMOS-level voltage to the X1 pin.
Preliminary Data Sheet U13995EJ1V0DS00
65
PD703100-33, 703100-40, 703101-33, 703102-33
DC Characteristics (TA = -40 to +70C ... PD703100-40,TA = -40 to +85C ... PD703100-33, PD703101-33,
PD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 10%, VSS=0 V)
Parameter High-level input voltage Symbol VIH Condition Except Note 1 Note 1 Low-level input voltage VIL Except Note 1 and Note 2 Note 1 High-level clock input voltage VXH X1 pin Direct mode PLL mode Low-level clock input voltage VXL X1 pin Direct mode PLL mode Schmitt-triggered input threshold voltage Schmitt-triggered input hysteresis width High-level output voltage HVT HVT
+
MIN. 2.2 0.8HVDD -0.5 -0.5 0.8VDD 0.8VDD -0.3 -0.3
TYP.
MAX. HVDD + 0.3 HVDD + 0.3 +0.8 0.2HVDD VDD + 0.3 VDD + 0.3 0.15VDD 0.15VDD
Unit V V V V V V V V V V V
Note 1, rising edge Note 1, falling edge Note 1 IOH = -2.5 mA IOH = -100 A 0.5
3.0 2.0
-
+
HVT -HVT- VOH
0.7HVDD HVDD - 0.4 0.45 10 -10
V V V
Low-level output voltage High-level input leakage current Low-level input leakage current High-level output leakage current Low-level output leakage current Analog pin input leakage current
VOL ILIH
IOL = 2.5 mA Except VI = HVDD or Note 2
A A A A A
ILIL
Except VI = 0 V or Note 2
ILOH
VO = HVDD
10 -10
ILOL
VO = 0 V
ILIAN
Note 2
T.B.D.
otes
1. P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/INTP130, P35/INTP131/SO2, P36/INTP132/S12, P37/INTP133/SCK2, P104/INTP120/TC0 to P107/INTP123/TC3, Pl14/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3, P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET 2. When the P70/ANI0 to P77/ANI7 pins are used as analog input.
Remark TYP. values are reference values for when TA = 25C, VDD = CVDD = 3.3 V, and HVDD = 5.0 V.
66
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
DC Characteristics (TA = -40 to +70C ... PD703100-40,TA = -40 to +85C ... PD703100-33, PD703101-33,
PD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 10%, VSS = 0 V)
Parameter Power supply current During normal operation Symbol IDD1 Condition Direct mode VDD + CVDD HVDD PLL mode VDD + CVDD MIN. TYP. 2.0 x fx 1.8 x fx 2.7 x fx - 17.0 1.3 x fx - 3.6 1.4 x fx 0.8 x fx 1.8 x fx - 10.0 0.8 x fx - 1.0 1.5 10 1.8 10 20 10 MAX. 3.6 x fx 3.0 x fx 3.6 x fx 3.0 x fx 2.5 x fx 1.6 x fx 2.5 x fx 1.6 x fx Unit mA mA mA
HVDD
mA
HALT mode
IDD2
Direct mode
VDD + CVDD HVDD
mA mA mA
PLL mode
VDD + CVDD
HVDD
mA
IDLE mode
IDD3
Direct mode
VDD + CVDD HVDD
3.0 50 3.0 50 100 50
mA
A
mA
PLL mode
VDD + CVDD HVDD
A A A
STOP mode
IDD4
VDD + CVDD HVDD
Remarks 1. TYP. values are reference values for when TA = 25C, VDD = CVDD = 3.3 V, and HVDD = 5.0 V. 2. Direct mode: fX = 2 to 40 MHz (PD703100-40) fX = 2 to 33 MHz (PD703100-33, PD703101-33, PD703102-33) PLL mode: fX = 20 to 40 MHz (PD703100-40) fX = 20 to 33 MHz (PD703100-33, PD703101-33, PD703102-33)
Preliminary Data Sheet U13995EJ1V0DS00
67
PD703100-33, 703100-40, 703101-33, 703102-33
Data Hold Characteristics(TA = -40 to +70C ... PD703100-40, TA = -40 to +85C ... PD703100-33, PD703101 33, PD703102-33)
Parameter Data hold voltage Symbol VDDDR HVDDDR Condition STOP mode, VDD = VDDDR STOP mode, HVDD = HVDDDR VDD = VDDDR 200 MIN. 1.5 VDDDR TYP. MAX. 3.6 5.5 Unit V V
Data hold current Power supply voltage rise time Power supply voltage fall time Power supply voltage hold time (to STOP mode setting) STOP mode release signal input time Data hold high-level input voltage Data hold low-level input voltage
IDDDR tRVD
T.B.D.
T.B.D.
A s s
ms
tFVD tHVD
200 0
tDREL
0
ns
VIHDR
Note
0.8 HVDDDR
HVDDDR
V
VILDR
Note
0
0.2 HVDDDR
V
Note P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/INTP130, P35/INTP131/SO2, P114/INTP140, P36/INTP132/SI2, P37/INTP133/SCK2, Pl16/INTP142/SI3, P104/INTP120/TC0 to P107/INTP123/TC3, P115/INTP141/SO3, P117/INTP143/SCK3,
P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12,P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0 ,P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET Remark TYP. values are reference values for when TA = 25C.
STOP mode setting
VDD tFVD tHVD
VDDDR tRVD tDREL
HVDD
RESET (input)
VIHDR
NMI (input) (Released by falling edge)
VIHDR
NMI (input) (Released by rising edge) VILDR
68
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
AC Characteristics (TA = -40 to +70C ... PD703100-40, TA = -40 to +85C ... PD703100-33, PD703101-33,
PD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 10%, VSS = 0 V, output pin load capacitance: CL = 50 pF)
AC Test Input Waveform (a) P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/ INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to P107/INTP123/ TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3, P124/INTP150 to P126/ INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/ SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET
HVDD Input signal 0V 0.2HVDD
0.8HVDD
Test points
0.8HVDD 0.2HVDD
(b) Pins other than those listed in (a) above
2.4 V Input signal 0.4 V 0.8 V 2.2 V 2.2 V 0.8 V
Test points
AC Test Output Test Points
2.4 V Output Signal 0.8 V 2.4 V 0.8 V
Test points
Preliminary Data Sheet U13995EJ1V0DS00
69
PD703100-33, 703100-40, 703101-33, 703102-33
Load Condition
DUT (Measured Device) CL = 50 pF
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert a buffer or other element to reduce the devide's load capacitance 50 pF. (1) Clock timing
Parameter X1 input cycle Symbol <1> tCYX Direct mode Condition MIN. 12.5 15 MAX. 250 250 Unit ns ns
PD703100-40 PD703100-33, 703101-33, 703102-33 PD703100-40 PD703100-33, 703101-33, 703102-33
PLL mode
125 150
250 250
ns ns
X1 input high-level width
<2>
tWXH
Direct mode PLL mode
5 50 5 50 4 10 4 10 2 2 40 33
ns ns ns ns ns ns ns ns MHz MHz
X1 input low-level width
<3>
tWXL
Direct mode PLL mode
X1 input rise time
<4>
tXR
Direct mode PLL mode
X1 input fall time
<5>
tXF
Direct mode PLL mode
CPU operating frequency
-
PD703100-40 PD703100-33, 703101-33, 703102-33
CLKOUT output cycle CLKOUT input high-level width CLKOUT input low-level width CLKOUT input rise time CLKOUT input fall time CLKOUT output delay time from X1
<6> <7> <8> <9> <10> <11>
tCYK tWKH tWKL tKR tKF tDXK Direct mode
30 0.5T - 7 0.5T - 4
500
ns ns ns
5 5 T.B.D. T.B.D.
ns ns ns
Remark T = tCYK
Parameter Free-running oscillation frequency - Symbol Condition PLL mode TYP. T.B.D. Unit MHz
P
70
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
<1> <2> <4> X1 (PLL mode) <1> <2> <4> X1 (Direct mode) <5> <11> <11> <3> <5> <3>
CLKOUT (output) <9> <7> <6> <10> <8>
(2) Output waveform (other than X1, CLKOUT)
Parameter Output rise time Output fall time Symbol <12> <13> tOR tOF Condition MIN. MAX. 10 10 Unit ns ns
<12>
<13>
Signals other than X1, CLKOUT
Preliminary Data Sheet U13995EJ1V0DS00
71
PD703100-33, 703100-40, 703101-33, 703102-33
(3) Reset timing
Parameter RESET high-level width RESET low-level width Symbol <14> <15> tWRSH tWRSL When power supply is on, and STOP mode has been released Other than when power supply is on, and STOP mode has been released Condition MIN. 500 500 + TOS MAX. Unit ns ns
500
ns
Remark TOS: Oscillation stabilization time
<14> <15>
RESET (input)
72
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
Preliminary Data Sheet U13995EJ1V0DS00
73
PD703100-33, 703100-40, 703101-33, 703102-33
(4) SRAM, external ROM, or external I/O access timing (a) Access timing (SRAM, external ROM, or external I/O) (1/2)
Parameter Address, CSn output delay time (from CLKOUT ) Address, CSn output hold time (from CLKOUT ) RD, IORD delay time (from CLKOUT ) RD, IORD delay time (from CLKOUT ) UWR, LWR, IOWR delay time (from CLKOUT ) UWR, LWR, IOWR delay time (from CLKOUT ) BCYST delay time (from CLKOUT ) BCYST delay time (from CLKOUT ) WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) Data input setup time (to CLKOUT ) Data input hold time (from CLKOUT ) Data output delay time (from CLKOUT ) Data output hold time (from CLKOUT ) Symbol <16> tDKA Condition
MIN. MAX.
Unit ns
2
10
<17>
tHKA
2
10
ns
<18>
tDKRDL
2
14
ns
<19>
tHKRDH
2
14
ns
<20>
tDKWRL
2
10
ns
<21>
tHKWRH
2
10
ns
<22>
tDKBSL
2
10
ns
<23>
tHKBSH
2
10
ns
<24> <25> <26>
tSWK tHKW tSKID
15 2 18
ns ns ns
<27>
tHKID
2
ns
<28>
tDKOD
2
10
ns
<29>
tHKOD
2
10
ns
Remarks 1. Maintain at least one of the data input hold times tHKID and tHRDID. 2. n = 0 to 7
74
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(a) Access timing (SRAM, external ROM, or external I/O) (2/2)
T1 TW T2
CLKOUT (Output)
<16>
<17>
A0 to A23 (Output) CSn (Output)
<22>
<23>
BCYCT (Output)
<18>
<19>
RD, IORD (Output) [Read time] <20> <21>
UWR, LWR, IOWR (Output) [Write time] <26> <27>
D0 to 15 (I/O) [Read time]
<28>
<29>
D0 to 15 (I/O) [Write time] <25> <24> <24> <25>
WAIT (Input)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero. 2. The broken lines indicate high impedance. 3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
75
PD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (SRAM, external ROM, or external I/O) (1/2)
Parameter Data input setup time (to address) Data input setup time (to RD) RD, IORD low-level width RD, IORD high-level width RD, IORD delay time from address, CSn Address delay time from RD, IORD Data input hold time (from RD, IORD ) Data output delay time from RD, IORD WAIT setup time (to address) WAIT setup time (to BCYST ) WAIT hold time (to BCYST ) Symbol <30> <31> <32> <33> <34> tSAID tSRDID tWRDL tWRDH tDARD (1 + wD + w) T - 10 T - 10 0.5T - 10 Condition MIN. MAX. (1.5 + wD + w) T - 28 (1 + wD + w) T - 32 Unit ns ns ns ns ns
<35> <36> <37> <38> <39> <40>
tDRDA tHRDID tDRDOD tSAW tSBSW tHBSW Note Note Note
(0.5 + i) T - 10 0 (0.5 + i) T - 10 T - 25 T - 25 0
ns ns ns ns ns ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero. Remarks 1. T = tCYK 2. w: the number of waits due to WAIT. 3. wD: the number of waits due to the DWC1 and DWC2 registers. 4. i: the number of idle states that are inserted when a write cycle follows a read cycle. 5. Maintain at least one of the data input hold times tHKID and tHRDID. 6. n = 0 to 7
76
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (SRAM, external ROM, or external I/O) (2/2)
T1 TW T2
CLKOUT (Output)
A0 to A23 (Output) CSn (Output)
UWR, LWR, IOWR (Output)
<33>
<32>
<35>
RD, IORD (Output) <34> <31> <30> <36> <37>
D0 to 15 (I/O)
<38>
WAIT (Input)
<39>
<40>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero. 2. The broken lines indicate high impedance. 3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
77
PD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (SRAM, external ROM, or external I/O) (1/2)
Parameter WAIT setup time (to address) WAIT setup time (to BCYST ) WAIT hold time (from BCYST ) UWR, LWR, IOWR delay time from address, CSn Address setup time (to UWR, LWR, IOWR ) Address delay time from UWR, LWR, IOWR UWR, LWR, IOWR high-level width UWR, LWR, IOWR low-level width Data output setup time (to UWR, LWR, IOWR ) Data output hold time (from UWR, LWR, IOWR ) Symbol <38> <39> <40> <41> tSAW tSBSW tHBSW tDAWR Condition Note Note Note 0 0.5T - 10 MIN. MAX. T - 25 T - 25 Unit ns ns ns ns
<42>
tSAWR
(1.5 + wD + w) T - 10
ns
<43>
tDWRA
0.5T - 10
ns
<44> <45> <46>
tWWRH tWWRL tSODWR
T - 10 (1 + wD + w) T - 10 (1.5 + wD + w) T - 10
ns ns ns
<47>
tHWROD
0.5T - 10
ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero. Remarks 1. T = tCYK 2. w: the number of waits due to WAIT. 3. wD: the number of waits due to the DWC1 and DWC2 registers. 4. n = 0 to 7
78
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (SRAM, external ROM, or external I/O) (2/2)
T1 TW T2
CLKOUT (Output)
A0 to A23 (Output) CSn (Output)
RD, IORD (Output) <42> <45> <43>
<41> <44>
UWR, LWR, IOWR (Output) <46> <47>
D0 to 15 (I/O)
<38>
WAIT (Input)
<39>
<40>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero. 2. The broken lines indicate high impedance. 3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
79
PD703100-33, 703100-40, 703101-33, 703102-33
(d) DMA flyby transfer timing (SRAM external I/O transfer) (1/2)
Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) RD low-level width Symbol <24> <25> <32> tSWK tHKW tWRDL Condition
MIN. MAX.
Unit ns ns ns
15 2 (1 + wD + wF + w) T - 10 T - 10 0.5T - 10 (0.5 + i) T - 10 (0.5 + i) T - 10 Note Note Note 0 0.5T - 10 (1.5 + wD + w) T - 10 0.5T - 10 T - 25 T - 25
RD high-level width RD delay time from address, CSn Address delay time from RD Data output delay time from RD WAIT setup time (to address) WAIT setup time (to BCYST ) WAIT hold time (from BCYST ) IOWR delay time from address Address setup time (to IOWR ) Address delay time from UWR, LWR, IOWR IOWR high-level width IOWR low-level width RD delay time from IOWR
<33> <34> <35> <37> <38> <39> <40> <41> <42> <43>
tWRDH tDARD tDRDA tDRDOD tSAW tSBSW tHBSW tDAWR tSAWR tDWRA
ns ns ns ns ns ns ns ns ns ns
<44> <45> <48>
tWWRH tWWRL tDWRRD wF = 0 wF = 1
T - 10 (1 + wD + w) T - 10 0 T - 10 0.5T - 10 (0.5 + wF) T - 10
ns ns ns ns ns ns
IOWR delay time from DMAAKm DMAAKm delay time from IOWR
<49> <50>
tDDAWR tDWRDA
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero. Remarks 1. T = tCYK 2. w: the number of waits due to WAIT. 3. wD: the number of waits due to the DWC1 and DWC2 registers. 4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer. 5. i: the number of idle states that are inserted when a write cycle follows a read cycle. 6. n = 0 to 7, m = 0 to 3
80
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(d) DMA flyby transfer timing (SRAM external I/O transfer) (2/2)
T1 CLKOUT (Output) TW T2
A0 to A23 (Output) CSn (Output) <33> <32> <35>
RD (Output)
<34>
<48>
UWR, LWR (Output)
DMAAKm (Output)
<49>
<50>
IORD (Output) <42> <41> <44> IOWR (Output) <45> <43>
<37>
D0 to 15 (I/O) <38> <24> WAIT (Input) <40> <39> BCYST (Output) <25> <24> <25>
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and wF = 0. 2. The broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3
Preliminary Data Sheet U13995EJ1V0DS00
81
PD703100-33, 703100-40, 703101-33, 703102-33
(e) DMA flyby transfer timing (external I/O SRAM transfer) (1/2)
Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) IORD low-level width Symbol <24> <25> <32> tSWK tHKW tWRDL Condition MIN. 15 2 (1 + wD + wF + w) T - 10 T - 10 0.5T - 10 (0.5 + i) T - 10 (0.5 + i) T - 10 Note Note Note 0 0.5T - 10 (1.5 + wD + w) T - 10 0.5T - 10 T - 25 T - 25 MAX. Unit ns ns ns
IORD high-level width IORD delay time from address, CSn Address delay time from IORD Data output delay time from IORD WAIT setup time (to address) WAIT setup time (to BCYST ) WAIT hold time (from BCYST ) UWR, LWR delay time from address Address setup time (to UWR, LWR ) Address delay time from UWR, LWR, IOWR UWR, LWR high-level width UWR, LWR low-level width IORD delay time from UWR, LWR
<33> <34> <35> <37> <38> <39> <40> <41> <42> <43>
tWRDH tDARD tDRDA tDRDOD tSAW tSBSW tHBSW tDAWR tSAWR tDWRA
ns ns ns ns ns ns ns ns ns ns
<44> <45> <48>
tWWRH tWWRL tDWRRD wF = 0 wF = 1
T - 10 (1 + wD + w) T - 10 0 T - 10 0.5T - 10 0.5T - 10
ns ns ns ns ns ns
IORD delay time from DMAAKm DMAAKm delay time from IORD
<51> <52>
tDDARD tDRDDA
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero. Remarks 1. T = tCYK 2. w: the number of waits due to WAIT. 3. wD: the number of waits due to the DWC1 and DWC2 registers. 4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer. 5. i: the number of idle states that are inserted when a write cycle follows a read cycle. 6. n = 0 to 7, m = 0 to 3
82
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(e) DMA flyby transfer timing (external I/O SRAM transfer) (2/2)
T1 CLKOUT (Output) TW T2
A0 to A23 (Output) CSn (Output) <41> <44> UWR, LWR (Output) <42> <45> <43> <35>
<48>
RD (Output)
<51>
<52>
DMAAKm (Output)
IOWR (Output) <34> <33> IORD (Output) <32> <35>
<37>
D0 to 15 (I/O) <38> <24> WAIT (Input) <40> <39> BCYST (Output) <25> <24> <25>
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and wF = 0. 2. The broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3
Preliminary Data Sheet U13995EJ1V0DS00
83
PD703100-33, 703100-40, 703101-33, 703102-33
(5) Page ROM access timing (1/2)
Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) Data input setup time (to CLKOUT ) Data input hold time (from CLKOUT ) Off-page data input setup time (to address) Off-page data input setup time (to RD) Off-page RD low-level width RD high-level width Data input hold time (from RD) Data output delay time from RD On-page RD low-level width Symbol <24> <25> <26> tSWK tHKW tSKID Condition MIN. 15 2 18 MAX. Unit ns ns ns
<27>
tHKID
2
ns
<30>
tSAID
(1.5 + wD + w) T - 28
ns
<31> <32> <33> <36> <37> <53>
tSRDID tWRDL tWRDH tHRDID tDRDOD tWORDL (1 + wD + w) T - 10 0.5T - 10 0 (0.5 + i) T - 10 (1.5 + wPR + w) T - 10
(1 + wD + w) T - 32
ns ns ns ns ns ns
On-page data input setup time (to address) On-page data input setup time (to RD)
<54>
tSOAID
(1.5 + wPR + w) T - 28
ns
<55>
tSORDID
(1.5 + wPR + w) T - 32
ns
Remarks 1. T = tCYK 2. w: the number of waits due to WAIT. 3. wD: the number of waits due to the DWC1 and DWC2 registers. 4. wPR: the number of waits due to the PRC register. 5. i: the number of idle states that are inserted when a write cycle follows a read cycle. 6. Maintain at least one of the data input hold times tHKID and tHRDID.
84
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(5) Page ROM access timing (2/2)
T1 CLKOUT (Output) TDW TW T2 TO1 TPRW TW TO2
Off-page address Note CSn (Output)
On-page address Note <26> <30> UWR, LWR (Output) <33> <32> <31> RD (Output) <36> <26> <27> D0 to 15 (I/O) <25> <24> WAIT (Input) <24> <25> <24> <25> <24> <25> <27> <36> <53> <55> <37> <54>
BCYST (Output)
Note On-page and off-page addresses are as follows.
PRC register MA5 0 0 0 1 MA4 0 0 1 1 MA3 0 1 1 1
On-page Addresses A0, A1 A0 to A2 A0 to A3 A0 to A4
Off-page Addresses A2 to A23 A3 to A23 A4 to A23 A5 to A23
Remarks 1. This is the timing for the following case. Number of waits due to the DWC1 and DWC2 registers (TDW): 1 Number of waits due to the PRC register (TPRW) 2. The broken lines indicate high impedance. 3. n = 0 to 7 :1
Preliminary Data Sheet U13995EJ1V0DS00
85
PD703100-33, 703100-40, 703101-33, 703102-33
(6) DRAM access timing (a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3)
Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) Data input setup time (to CLKOUT ) Data input hold time (from CLKOUT ) Data output delay time from OE Row address setup time Row address hold time Column address setup time Column address hold time Read/write cycle time Symbol <24> <25> <26> <27> <37> <56> <57> <58> <59> <60> tSWK tHKW tSKID tHKID tDRDOD tASR tRAH tASC tCAH tRC Condition MIN. 15 2 18 2 (0.5 + i) T - 10 (0.5 + wRP) T - 10 (0.5 + wRH) T - 10 0.5T - 10 (1.5 + wDA + w) T - 10 (3 + wRP + wRH + wDA + w) T - 10 (0.5 + wRP) T - 10 (2.5 + wRH + wDA + w) T - 10 (1.5 + wDA + w) T - 10 (2 + wDA + w) T - 10 (1 + wDA + w) T - 10 (1 + wRP) T - 10 (2 + wRH + wDA + w) T - 10 (2 + wRP + wRH) T - 10 0.5T - 10 T - 10 (2 + wRP + wRH) T - 10 (2 + wRP + wRH + wDA + w) T - 28 (2 + wRH + wDA + w) T - 28 (1.5 + wDA + w) T - 28 (1 + wDA + w) T - 28 MAX. Unit ns ns ns ns ns ns ns ns ns ns
RAS precharge time RAS pulse time
<61> <62>
tRP tRAS
ns ns
RAS hold time Column address read time for RAS CAS pulse width CAS-RAS precharge time CAS hold time
<63> <64> <65> <66> <67>
tRSH tRAL tCAS tCRP tCSH
ns ns ns ns ns
WE setup time WE hold time (from RAS ) WE hold time (from CAS ) CAS precharge time Output enable access time
<68> <69> <70> <71> <72>
tRCS tRRH tRCH tCPN tOEA
ns ns ns ns ns
RAS access time
<73>
tRAC
ns
Access time from column address CAS access time
<74> <75>
tAA tCAC
ns ns
Remarks 1. T = tCYK 2. w: the number of waits due to WAIT. 3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. i: the number of idle states that are inserted when a write cycle follows a read cycle.
86
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(a) Read timing (high-speed page DRAM access, normal access: off-page) (2/3)
Parameter RAS column address delay time RAS-CAS delay time Output buffer turn-off delay time (from OE ) Output buffer turn-off delay time (from CAS ) Symbol <76> <77> <78> tRAD tRCD tOEZ Condition
MIN. MAX.
Unit ns ns ns
(0.5 + wRH) T - 10 (1 + wRH) T - 10 0
<79>
tOFF
0
Remarks 1. T = tCYK 2. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
Preliminary Data Sheet U13995EJ1V0DS00
87
PD703100-33, 703100-40, 703101-33, 703102-33
(a) Read timing (high-speed page DRAM access, normal access: off-page) (3/3)
TRPW CLKOUT (Output) <58> <56> <57> <59> T1 TRHW T2 TDAW TW T3
A0 to A23 (Output)
Row address
Column address <63> <64> <62>
<76> <61>
RASn (Output) <60> <77> <66> UCAS (Output) LCAS (Output) <71> <73> <68> <75> <70> <69> <67> <65>
WE (Output) <74> <72> <27> <37> <79>
OE (Output) <78> <26>
D0 to D15 (I/O) <24> <25> <24> <25>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1 Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 2. The broken lines indicate high impedance. 3. n = 0 to 7
88
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
Preliminary Data Sheet U13995EJ1V0DS00
89
PD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (high-speed page DRAM access: on-page) (1/2)
Parameter Data input setup time (to CLKOUT ) Data input hold time (from CLKOUT ) Data output delay time from OE Column address setup time Column address hold time RAS hold time Column address read time for RAS CAS pulse width WE setup time (to CAS ) WE hold time (from RAS ) WE hold time (from CAS ) Output enable access time Access time from column address CAS access time Output buffer turn-off delay time (from OE ) Output buffer turn-off delay time (from CAS ) Access time from CAS precharge CAS precharge time High-speed page mode cycle time RAS hold time for CAS precharge Symbol <26> <27> <37> <58> <59> <63> <64> <65> <68> <69> <70> <72> <74> <75> <78> tSKID tHKID tDRDOD tASC tCAH tRSH tRAL tCAS tRCS tRRH tRCH tOEA tAA tCAC tOEZ 0 Condition MIN. 18 2 (0.5 + i) T - 10 (0.5 + wCP) T - 10 (1.5 + wDA) T - 10 (1.5 + wDA) T - 10 (2 + wCP + wDA) T - 10 (1 + wDA) T - 10 (1 + wCP) T - 10 0.5T - 10 T - 10 (1 + wCP + wDA) T - 28 (1.5 + wCP + wDA) T - 28 (1 + wDA) T - 28 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
<79>
tOFF
0
ns
<80> <81> <82> <83>
tACP tCP tPC tRHCP (1 + wCP) T - 10 (2 + wCP + wDA) T - 10 (2.5 + wCP + wDA) T - 10
(2 + wCP + wDA) T - 28
ns ns ns ns
Remarks 1. T = tCYK 2. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. i: the number of idle states that are inserted when a write cycle follows a read cycle.
90
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (high-speed page DRAM access: on-page) (2/2)
TCPW CLKOUT (Output) TO1 TDAW TO2
<58>
<59>
A0 to A23 (Output)
Column address <63> <64>
RASn (Output) <83> <81> <65> <82> UCAS (Output) LCAS (Output) <69> <68> WE (Output) <75> <72> <26> <79> <37> <70>
OE (Output)
<74> <80> D0 to D15 (I/O)
<78> <27>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 2. The broken lines indicate high impedance. 3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
91
PD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2)
Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) Row address setup time Row address hold time Column address setup time Column address hold time Read/write cycle time Symbol <24> <25> <56> <57> <58> <59> <60> tSWK tHKW tASR tRAH tASC tCAH tRC Condition MIN. 15 2 (0.5 + wRP) T - 10 (0.5 + wRH) T - 10 0.5T - 10 (1.5 + wDA + w) T - 10 (3 + wRP + wRH + wDA + w) T - 10 (0.5 + wRP) T - 10 (2.5 + wRH + wDA + w) T - 10 (1.5 + wDA + w) T - 10 (2 + wDA + w) T - 10 (1 + wDA + w) T - 10 (1 + wRH) T - 10 (2 + wRH + wDA + w) T - 10 (2 + wRP + wRH) T - 10 (0.5 + wRH) T - 10 (1 + wRH) T - 10 (1 + wRP + wRH ) T - 10 (1 + wDA + w) T - 10 (1.5 + wRP + wRH) T - 10 (1.5 + wDA + w) T - 10 MAX. Unit ns ns ns ns ns ns ns
RAS precharge time RAS pulse time
<61> <62>
tRP tRAS
ns ns
RAS hold time Column address read time (from RAS ) CAS pulse width CAS-RAS precharge time CAS hold time
<63> <64> <65> <66> <67>
tRSH tRAL tCAS tCRP tCSH
ns ns ns ns ns
CAS precharge time RAS column address delay time RAS-CAS delay time WE setup time (to CAS ) WE hold time (from CAS ) Data setup time (to CAS ) Data hold time (from CAS )
<71> <76> <77> <84>
tCPN tRAD tRCD tWCS
ns ns ns ns
<85> <86> <87>
tWCH tDS tDH
ns ns ns
Remarks 1. T = tCYK 2. w: the number of waits due to WAIT. 3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
92
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (high-speed page DRAM access, normal access: off-page) (2/2)
TRPW CLKOUT (Output) <58> <56> <57> <59> T1 TRHW T2 TDAW TW T3
A0 to A23 (Output)
Row address
Column address <63> <64> <62>
<76> <61>
RASn (Output) <60> <77> <66> UCAS (Output) LCAS (Output) <71> <67> <65>
OE (Output)
<84>
<85>
WE (Output)
<86>
<87>
D0 to D15 (I/O) <24> <25> <24> <25>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1 Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 2. The broken lines indicate high impedance. 3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
93
PD703100-33, 703100-40, 703101-33, 703102-33
(d) Write timing (high-speed page DRAM access: on-page) (1/2)
Parameter Column address setup time Column address hold time RAS hold time Column address read time (from RAS ) CAS pulse width CAS precharge time RAS hold time for CAS precharge WE setup time (to CAS ) WE hold time (from CAS ) Data setup time (to CAS ) Data hold time (from CAS ) WE read time (from RAS ) WE read time (from CAS ) Data setup time (to WE ) Data hold time (from WE ) WE pulse width Symbol <58> <59> <63> <64> <65> <81> <83> tASC tCAH tRSH tRAL tCAS tCP tRHCP wCP 1 Condition MIN. (0.5 + wCP) T - 10 (1.5 + wDA) T - 10 (1.5 + wDA) T - 10 (2 + wCP + wDA) T - 10 (1 + wDA) T - 10 (1 + wCP) T - 10 (2.5 + wCP + wDA) T - 10 wCPT - 10 (1 + wDA) T - 10 (0.5 + wCP) T - 10 (1.5 + wDA) T - 10 wCP = 0 wCP = 0 wCP = 0 wCP = 0 wCP = 0 (1.5 + wDA) T - 10 (1 + wDA) T - 10 0.5T - 10 (1.5 + wDA) T - 10 (1 + wDA) T - 10 MAX. Unit ns ns ns ns ns ns ns
<84> <85> <86> <87> <88> <89> <90> <91> <92>
tWCS tWCH tDS tDH tRWL tCWL tDSWE tDHWE tWP
ns ns ns ns ns ns ns ns ns
Remarks 1. T = tCYK 2. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
94
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(d) Write timing (high-speed page DRAM access: on-page) (2/2)
TCPW CLKOUT (Output) TO1 TDAW TO2
<58>
<59>
A0 to A23 (Output)
Column address <63> <64>
RASn (Output) <83> <81> UCAS (Output) LCAS (Output) <89> <88> <65>
OE (Output) <84> <92> <85>
WE (Output) <91> <90> <86> D0 to D15 (I/O) <87>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the CPCxx bit of the DRCn register (TCPW ): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 2. The broken lines indicate high impedance. 3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
95
PD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (1/3)
Parameter Data input setup time (to CLKOUT ) Data input hold time (from CLKOUT ) Data output delay time from OE Row address setup time Row address hold time Column address setup time Column address hold time RAS precharge time Column address read time (from RAS ) CAS-RAS precharge time CAS hold time WE setup time (to CAS ) WE hold time (from RAS ) WE hold time (from CAS ) RAS access time Access time from column address CAS access time Column address delay time from RAS RAS-CAS delay time Output buffer turn-off delay time (from OE) Access time from CAS precharge CAS precharge time RAS hold time for CAS precharge Read cycle time RAS pulse width CAS pulse width CAS hold time from OE Off-page On-page Data input hold time (from CAS ) Symbol <26> <27> <37> <56> <57> <58> <59> <61> <64> <66> <67> <68> <69> <70> <73> <74> <75> <76> <77> <78> tSKID tHKID tDRDOD tASR tRAH tASC tCAH tRP tRAL tCRP tCSH tRCS tRRH tRCH tRAC tAA tCAC tRAD tRCD tOEZ (0.5 + wRH) T - 10 (1 + wRH) T - 10 0 Condition MIN. 18 2 (0.5 + i) T - 10 (0.5 + wRP) T - 10 (0.5 + wRH) T - 10 0.5T - 10 (0.5 + wDA) T - 10 (0.5 + wRP) T - 10 (2 + wCP + wDA) T - 10 (1 + wRP) T - 10 (1.5 + wRH + wDA) T - 10 (2 + wRP + wRH) T - 10 0.5T - 10 1.5T - 10 (2 + wRH + wDA) T - 28 (1.5 + wDA) T - 28 (1 + wDA) T - 28 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
<80> <81> <83> <93> <94> <95> <96> <97> <98>
tACP tCP tRHCP tHPC tRASP tHCAS tOCH1 tOCH2 tDHC (0.5 + wCP) T - 10 (2 + wCP + wDA) T - 10 (1 + wDA + wCP) T - 10 (2.5 + wRH + wDA) T - 10 (0.5 + wDA) T - 10 (2 + wRH + wDA) T - 10 (0.5 + wDA) T - 10 0
(1.5 + wCP + wDA) T - 28
ns ns ns ns ns ns ns ns ns
Remarks 1. T = tCYK 2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. i: the number of idle states that are inserted when a write cycle follows a read cycle.
96
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (2/3)
Parameter Output enable access time Off-page Symbol <99> tOEA1 Condition MIN. MAX. (2 + wPR + wRH + wDA) T - 28 (1 + wCP + wDA) T - 28 Unit ns
On-page
<100>
tOEA2
ns
Remarks 1. T = tCYK 2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
Preliminary Data Sheet U13995EJ1V0DS00
97
PD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (3/3)
TRPW CLKOUT (Output) <58> <56> A0 to A23 (Output) <57> <59>
Column address Column address
T1
TRHW
T2
TDAW TCPW
TB
TDAW
TE
Row address <76> <61>
<64> <74> <94>
RASn (Output) <67> <66> UCAS (Output) LCAS (Output) <68> <93> <80> WE (Output) <97> <96> OE (Output) <75> <74> D0 to D15 (I/O) <73> <99> BCYST (Output) <26> Data <98> <27> <27> <78> Data <100> <26> <37> <95> <69> <70> <77> <95> <81> <83> <75>
WAIT (Input)
Note For on-page access from another cycle during the RASn low level signal. Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1 Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1 2. The broken lines indicate high impedance. 3. n = 0 to 7
98
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
Preliminary Data Sheet U13995EJ1V0DS00
99
PD703100-33, 703100-40, 703101-33, 703102-33
(f) Write timing (EDO DRAM) (1/2)
Parameter Row address setup time Row address hold time Column address setup time Column address hold time RAS precharge time RAS hold time Column address read time (from RAS ) CAS-RAS precharge time CAS hold time Column address delay time from RAS RAS-CAS delay time CAS precharge time RAS hold time for CAS precharge WE hold time (from CAS ) Data hold time (from CAS ) WE read time (from RAS ) WE read time (from CAS ) WE pulse width Write cycle time RAS pulse width CAS pulse width WE setup time (to CAS ) Data setup time (to CAS ) Off-page On-page Off-page On-page On-page Symbol <56> <57> <58> <59> <61> <63> <64> tASR tRAH tASC tCAH tRP tRSH tRAL Condition MIN. (0.5 + wRP) T - 10 (0.5 + wRH) T - 10 0.5T - 10 (0.5 + wDA) T - 10 (0.5 + wRP) T - 10 (1.5 + wDA) T - 10 (2 + wCP + wDA) T - 10 MAX. Unit ns ns ns ns ns ns ns
<66> <67> <76> <77> <81> <83> <85> <87> <88>
tCRP tCSH tRAD tRCD tCP tRHCP tWCH tDH tRWL wCP = 0
(1 + wRP) T - 10 (1.5 + wRH + wDA) T - 10 (0.5 + wRH) T - 10 (1 + wRH) T - 10 (0.5 + wCP) T - 10 (2 + wCP + wDA) T - 10 (1 + wDA) T - 10 (0.5 + wDA) T - 10 (1.5 + wDA) T - 10
ns ns ns ns ns ns ns ns ns
On-page
<89>
tCWL
wCP = 0
(0.5 + wDA) T - 10
ns
On-page
<92> <93> <94> <95> <101> <102> <103> <104>
tWP tHPC tRASP tHCAS tWCS1 tWCS2 tDS1 tDS2
wCP = 0
(1 + wDA) T - 10 (1 + wDA + wCP) T - 10 (2.5 + wRH + wDA) T - 10 (0.5 + wDA) T - 10 (1 + wRP + wRH) T - 10
ns ns ns ns ns ns ns ns
wCP 1
wCPT - 10 (1.5 + wRP + wRH) T - 10 (0.5 + wCP) T - 10
Remarks 1. T = tCYK 2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
100
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(f) Write timing (EDO DRAM) (2/2)
TRPW CLKOUT (Output) <58> <56> A0 to A23 (Output) <57> <59> Column address <58> <59> Column address <64> <94> T1 TRHW T2 TDAW TCPW TB TDAW TE
Row address <76> <61>
RASn (Output) <67> <66> UCAS (Output) LCAS (Output) <93> <89> <88> RD (Output) OE (Output) <102> <101> <92> WE (Output) <85> <85> <95> <77> <95> <81> <83> <63>
<103>
<87>
<104>
<87>
D0 to D15 (I/O)
Data
Data
BCYST (Output)
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1 Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1 2. The broken lines indicate high impedance. 3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
101
PD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) external I/O transfer) (1/3)
Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) Data output delay time from OE IOWR delay time from address Address setup time (to UWR, LWR IOWR ) Address delay time from IOWR RD delay time from IOWR Symbol <24> <25> <37> <41> <42> tSWK tHKW tDRDOD tDAWR tSAWR Condition MIN. 15 2 (0.5 + i) T - 10 (0.5 + wRP) T - 10 (2 + wRP + wRH + wDA) T - 10 0.5T - 10 wF = 0 wF = 1 IOWR low-level width <50> tWWRL 0 T - 10 (2 + wRH + wDA + w) T - 10 (0.5 + wRP) T - 10 (0.5 + wRH) T - 10 0.5T - 10 (1.5 + wDA + wF + w) T - 10 (3 + wRP + wRH + wDA + wF +w) T - 10 (0.5 + wRP) T - 10 (1.5 + wDA + wF + w) T - 10 (2 + wCP + wDA + wF + w) T - 10 (1 + wDA + wF + w) T - 10 (1 + wRP) T - 10 (2 + wRH + wDA + wF +w) T - 10 (2 + wRP + wRH) T - 10 0.5T - 10 1.5T - 10 (2 + wRP + wRH) T - 10 (0.5 + wRH) T - 10 (1 + wRH) T - 10 MAX. Unit ns ns ns ns ns
<43> <48>
tDWRA tDWRRD
ns ns ns ns
Row address setup time Row address hold time Column address setup time Column address hold time
<56> <57> <58> <59>
tASR tRAH tASC tCAH
ns ns ns ns
Read/write cycle time
<60>
tRC
ns
RAS precharge time RAS hold time
<61> <63>
tRP tRSH
ns ns
Column address read time for RAS
<64>
tRAL
ns
CAS pulse width
<65>
tCAS
ns
CAS-RAS precharge time CAS hold time WE setup time (to CAS ) WE hold time (from RAS ) WE hold time (from CAS ) CAS precharge time RAS column address delay time RAS-CAS delay time
<66> <67>
tCRP tCSH
ns ns
<68> <69> <70> <71> <76> <77>
tRCS tRRH tRCH tCPN tRAD tRCD
ns ns ns ns ns ns
102
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Remarks 1. T = tCYK 2. w: the number of waits due to WAIT. 3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer. 8. i: the number of idle states that are inserted when a write cycle follows a read cycle.
Preliminary Data Sheet U13995EJ1V0DS00
103
PD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) R external I/O transfer) (2/3)
Parameter Output buffer turn-off delay time (from OE ) Output buffer turn-off delay time (from CAS ) CAS precharge time High-speed page mode cycle time Symbol <78> tOEZ Condition MIN. 0 MAX. Unit ns
<79>
tOFF
0
ns
<81> <82>
tCP tPC
(0.5 + wCP) T - 10 (2 + wCP + wDA + wF + w) T - 10 (2.5 + wCP + wDA + wF + w) T - 10 (2.5 + wRH + wDA + wF + w) T - 10 (2.5 + wRP + wRH + wDA + wF + w) T - 10 (1.5 + wCP + wDA + wF + w) T - 10 (1.5 + wRH) T - 10 (1 + wRH) T - 10
ns ns
RAS hold time for CAS precharge
<83>
tRHCP
ns
RAS pulse width OE CAS hold time (from CAS )
<94>
tRASP
ns
Off-page
<96>
tOCH1
ns
On-page CAS delay time from DMAAKm CAS delay time from IOWR
<97>
tOCH2
ns
<105> <106>
tDDACS tDRDCS
ns ns
Remarks 1. T=tCYK 2. w: the number of waits due to WAIT. 3. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer. 8. m = 0 to 3
104
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) external I/O transfer) (3/3)
TRPW
T1
TRHW
T2
TDAW
TW
T3
TCPW TO1 TDAW
TW
TO2
CLKOUT (Output)
<58> <56> <57> <59>
A0 to A23 (Output)
Row address
<76> <61>
Column address
<94> <60>
Column address
<64>
RASn (Output)
<77> <66> <67> <65> <81> <83> <63> <69>
UCAS (Output) LCAS (Output)
<71> <96> <82> <70> <79>
RD (Output) OE (Output)
<105> <48> <97>
DMAAKm (Output)
<68>
WE (Output)
IORD (Output)
<41>
<106> <42> <50>
<43>
<78> <37>
IOWR (Output)
<24>
D0 to D15 (I/O)
<25> <24>
Data <24> <25> <25>
Data
WAIT (Input)
BCYST (Output)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1 Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1 Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0 2. The broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3
Preliminary Data Sheet U13995EJ1V0DS00
105
PD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O DRAM (EDO, high-speed page) transfer) (1/3)
Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) IORD low-level width IORD high-level width IORD delay time from address, CSn Address delay time from IORD Row address setup time Row address hold time Column address setup time Column address hold time Read/write cycle time Symbol <24> <25> <32> <33> <34> <35> <56> <57> <58> <59> <60> tSWK tHKW tWRDL tWRDH tDARD tDRDA tASR tRAH tASC tCAH tRC Condition MIN. 15 2 (2 + wRH + wDA + wF + w) T - 10 T - 10 0.5T - 10 (0.5 + i) T - 10 (0.5 + wRP) T - 10 (0.5 + wRH) T - 10 0.5T - 10 (1.5 + wDA + wF) T - 10 (3 + wRP + wRH + wDA + wF + w) T - 10 (0.5 + wRP) T - 10 (1.5 + wDA + wF) T - 10 (2 + wCP + wDA + wF + w) T - 10 (1 + wDA + wF) T - 10 (1 + wRP) T - 10 (2 + wRH + wDA + wF + w) T - 10 (2 + wRP + wRH + w) T - 10 (0.5 + wRH) T - 10 (1 + wRH + w) T - 10 (0.5 + wCP + w) T - 10 (2 + wCP + wDA + wF + w) T - 10 (2.5 + wCP + wDA + w) T - 10 (1 + wDA) T - 10 wCP = 0 wCP = 0 wCP = 0 (1.5 + wDA + w) T - 10 (1 + wDA + w) T - 10 (1 + wDA + w) T - 10 (2.5 + wRH + wDA + wF + w) T - 10 wCP = 0 wCP 1 (1 + wRH + wRP + w) T - 10 wCPT - 10 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
RAS precharge time RAS hold time Column address read time for RAS CAS pulse width CAS-RAS precharge time CAS hold time CAS precharge time RAS column address delay time RAS-CAS delay time CAS precharge time High-speed page mode cycle time RAS hold time for CAS precharge WE hold time (from CAS ) WE read time (from RAS ) WE read time (from CAS ) WE pulse width RAS pulse width WE setup time (to CAS ) Off-page On-page
<61> <63> <64> <65> <66> <67> <71> <76> <77> <81> <82> <83> <85> <88> <89> <92> <94> <101> <102>
tRP tRSH tRAL tCAS tCRP tCSH tCPN tRAD tRCD tCP tPC tRHCP tWCH tRWL tCWL tWP tRASP tWCS1 tWCS2
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
106
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Remarks 1. T = tCYK 2. w: the number of waits due to WAIT. 3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer. 8. i: the number of idle states that are inserted when a write cycle follows a read cycle. 9. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
107
PD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O DRAM (EDO, high-speed page) transfer) (2/3)
Parameter CAS delay time from DMAAKm CAS delay time from IORD IORD delay time from WE Symbol <105> <106> <107> tDDACS tDRDCS tDWERD wF= 0 wF= 1 Condition
MIN. MAX.
Unit ns ns ns ns
(1.5 + wRH + w) T - 10 (1 + wRH + w) T - 10 0 T - 10
Remarks 1. T = tCYK 2. w: the number of waits due to WAIT. 3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer. 5. m = 0 to 3
108
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O DRAM (EDO, high-speed page) transfer) (3/3)
TRPW
T1
TRHW
TW
T2
TDAW
T3
TCPW
TW
TO1 TDAW TO2
CLKOUT (Output)
<56> <57> <58> <59>
A0 to A23 (Output)
Row address
<76> <61>
Column address
<94> <60>
Column address
<64>
RASn (Output)
<77> <66> <67> <65>
<81>
<63>
UCAS (Output) LCAS (Output)
<71> <82> <83>
RD (Output) OE (Output)
<101> <85>
<102> <88> <89>
WE (Output)
<105> <92>
DMAAKm (Output)
IOWR (Output)
<106> <34> <107> <35>
IORD (Output)
<32> <25> <33> Data <24> <24> <25> <24> <25> Data
D0 to D15 (I/O)
WAIT (Input)
BCYST (Output)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1 Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1 Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0 2. The broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3
Preliminary Data Sheet U13995EJ1V0DS00
109
PD703100-33, 703100-40, 703101-33, 703102-33
(i) CBR refresh timing
Parameter RAS precharge time RAS pulse width CAS hold time REFRQ pulse width RAS precharge CAS hold time REFRQ active delay time (from CLKOUT ) REFRQ inactive delay time (from CLKOUT ) CAS setup time Symbol <61> <62> <108> <109> <110> <111> tRP tRAS tCHR tWRFL tRPC tDKRF Condition MIN. (1.5 + wRRW) T - 10 (1.5 + wRCW (1.5 + wRCW
Note
MAX.
Unit ns ns ns ns ns
) T - 10 ) T - 10
Note
Note
(3 + wRRW + wRCW
) T - 10
(0.5 + wRRW) T - 10 2 10
ns
<112>
tHKRF
2
10
ns
<113>
tCSR
T - 10
ns
Note At least one clock cycle is inserted by default for wRCW regardless of the settings of the RCW0 to RCW2 bits of the RWC register. Remarks 1. T = tCYK 2. wRRW: the number of waits due to the RRW0 and RRW1 bits of the RWC register. 3. wRCW: the number of waits due to the RCW0 to RCW2 bits of the RWC register.
TRRW CLKOUT (Output) <111> <109> REFRQ (Output) <112> T1 T2 TRCWNote TRCW T3 TI
<61>
<62>
RASn (Output) <110> <110> UCAS (Output) LCAS (Output) <113> <108>
Note This TRCW is always inserted regardless of the settings of the RCW0 to RCW2 bits of the RWC register. Remarks 1. This is the timing for the following case. Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1 Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 2 2. n = 0 to 7
110
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(j) CBR self-refresh timing
Parameter REFRQ active delay time (from CLKOUT ) REFRQ inactive delay time (from CLKOUT ) CAS hold time RAS precharge time Symbol <111> tDKRF Condition MIN. 2 MAX. 10 Unit ns
<112>
tHKRF
2 -5 (1 + 2wSRW) T - 10
10
ns
<114> <115>
tCHS tRPS
ns ns
Remarks 1. T = tCYK 2. wSRW: the number of waits due to the SRW0 to SRW2 bits of the RWC register.
TRRW CLKOUT (Output) TH TH TH TRCW TH TI TSRW TSRW
<111>
<112>
REFRQ (Output)
<115>
RASn (Output)
<114>
UCAS (Output) LCAS (Output)
Output signals other than above
Remarks 1. This is the timing for the following case. Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1 Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 1 Number of waits due to the SRW0 to SRW2 bits of the RWC register (TSRW): 2 2. The broken lines indicate high impedance. 3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
111
PD703100-33, 703100-40, 703101-33, 703102-33
(7) DMAC timing
Parameter DMARQn setup time (to CLKOUT ) DMARQn hold time (from CLKOUT ) Symbol <116> <117> <118> DMAAKn output delay time (from CLKOUT ) DMAAKn output hold time (from CLKOUT ) TCn output delay time (from CLKOUT ) TCn output hold time (from CLKOUT ) <119> tSDRK tHKDR1 tHKDR2 tDKDA Condition
MIN. MAX.
Unit ns ns ns
15 2 Until DMAAKn 2 10
ns
<120>
tHKDA
2
10
ns
<121>
tDKTC
2
10
ns
<122>
tHKTC
2
10
ns
Remark n = 0 to 3
CLKOUT (Output) <117> <116> DMARQn (Input) <116> <119> DMAAKn (Output) <120> <118>
<122> <121> TCn (Output)
Remark n = 0 to 3
112
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
Preliminary Data Sheet U13995EJ1V0DS00
113
PD703100-33, 703100-40, 703101-33, 703102-33
(8) Bus hold timing (1/2)
Parameter HLDRQ setup time (to CLKOUT ) HLDRQ hold time (from CLKOUT ) HLDAK delay time from CLKOUT HLDRQ high-level width HLDAK low-level width Bus float delay time from CLKOUT Bus output delay time from HLDAK HLDAK delay time from HLDRQ HLDAK delay time from HLDRQ Symbol <123> <124> <125> <126> <127> <128> <129> <130> <131> tSHRK tHKHR tDKHA tWHQH tWHAL tDKCF tDHAC tDHQHA1 tDHQHA2 0 2.5T 0.5T 1.5T Condition MIN. 15 2 2 T + 17 T-8 10 10 MAX. Unit ns ns ns ns ns ns ns ns ns
Remark T = tCYK
114
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(8) Bus hold timing (2/2)
T1
CLKOUT (Output)
<123> <123> <124> <123> <124> <123> <126>
T2
T3
TI
TH
TH
TH
TI
T1
HLDRQ (Intput)
<125> <130> <125> <131>
HLDAK (Output)
<127> <128> <129>
A0 to A23 (Output)
Address
Undefined
D0 to D15 (I/O)
Data
CSn/RASn (Output)
BCYST (Output)
RD (Output)
WE (Output)
UCAS (Output) LCAS (Output)
WAIT (Input)
Remarks 1. The broken lines indicate high impedance. 2. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
115
PD703100-33, 703100-40, 703101-33, 703102-33
(9) Interrupt timing
Parameter NMI high-level width NMI low-level width INTPn high-level width INTPn low-level width Symbol <132> <133> <134> <135> tWNIH tWNIL tWITH tWITL Condition MIN. 500 500 4T + 10 4T + 10 MAX. Unit ns ns ns ns
Remarks 1. n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153 2. T = tCYK
<132> <133>
NMI (Input)
<134>
<135>
INTPn (Input)
Remark n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153 (10) RPU timing
Parameter TI1n high-level width TI1n low-level width TCLR1n high-level width TCLR1n low-level width Symbol <136> <137> <138> <139> tWTIH tWTIL tWTCH tWTCL Condition MIN. 3T + 18 3T + 18 3T + 18 3T + 18 MAX. Unit ns ns ns ns
Remarks 1. n = 0 to 5 2. T = tCYK
<136> <137>
TI1n (Input)
<138>
<139>
TCLR1n (Input)
Remark n = 0 to 5
116
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
(11) UART0, UART1 timing (clock-synchronized or master mode only)
Parameter SCKn cycle SCKn high-level width SCKn low-level width RXDn setup time (to SCKn ) RXDn hold time (from SCKn ) TXDn output delay time (from SCKn ) TXDn output hold time (from SCKn ) Symbol <140> <141> <142> <143> <144> <145> <146> tCYSK0 tWSK0H tWSK0L tSRXSK tHSKRX tDSKTX tHSKTX 0.5tCYSK0 - 5 Condition Output Output Output MIN. 250 0.5tCYSK0 - 20 0.5tCYSK0 - 20 30 0 20 MAX. Unit ns ns ns ns ns ns ns
Remark n = 0, 1
<140> <142> <141>
SCKn (I/O)
<143>
<144>
RXDn (Input)
Input data
<145>
<146>
TXDn (Output)
Output data
Remarks 1. The broken lines indicate high impedance. 2. n = 0, 1
Preliminary Data Sheet U13995EJ1V0DS00
117
PD703100-33, 703100-40, 703101-33, 703102-33
(12) CSI0 to CSI3 timing (a) Master mode
Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn ) SIn hold time (from SCKn ) SOn output delay time (from SCKn ) SOn output hold time (from SCKn ) Symbol <147> <148> <149> <150> <151> <152> <153> tCYSK1 tWSK1H tWSK1L tSSISK tHSKSI tDSKSO tHSKSO 0.5tCYSK1 - 5 Condition Output Output Output MIN. 100 0.5tCYSK1 - 20 0.5tCYSK1 - 20 30 0 20 MAX. Unit ns ns ns ns ns ns ns
Remark n = 0 to 3 (b) Slave mode
Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn ) SIn hold time (from SCKn ) SOn output delay time (from SCKn ) SOn output hold time (from SCKn ) Symbol <147> <148> <149> <150> <151> <152> <153> tCYSK1 tWSK1H tWSK1L tSSISK tHSKSI tDSKSO tHSKSO tWSK1H Condition Input Input Input MIN. 100 30 30 10 10 30 MAX. Unit ns ns ns ns ns ns ns
Remark n = 0 to 3
<147> <149> <148>
SCKn (I/O)
<150>
<151>
Sln (Input)
Input data
<152>
<153>
SOn (Output)
Output data
Remarks 1. The broken lines indicate high impedance. 2. n = 0 to 3
118
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
A/D Converter Characteristics (TA = -40 to +70C ... PD703100-40, TA = -40 to +85C ... PD703100-33,
PD703101-33, PD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V 10%, VSS = 0 V, HVDD - 0.5 V < AVDD < HVDD, output pin load capacitance: CL = 50
pF)
Parameter Resolution Total error Quantization error Conversion time Sampling time Zero scale error Full scale error Nonlinearity error Analog input voltage Analog input resistance AVREF input voltage AVREF input current AVDD current Symbol - - - tCONV tSAMP - - - VIAN RAN AVREF AIREF AIDD AVREF = AVDD 4.5 -0.3 2 5.5 1.6 6 5 833 2 2 1 AVREF + 0.3 Condition MIN. 10 4 1/2 TYP. MAX. Unit bit LSB LSB
s
ns LSB LSB LSB V M V mA mA
Preliminary Data Sheet U13995EJ1V0DS00
119
PD703100-33, 703100-40, 703101-33, 703102-33
17. PACKAGE DRAWING
144 PIN PLASTIC LQFP (FINE PITCH) (20 20)
A B
108 109 73 72
detail of lead end
C
D
S R Q
144 1
37 36
F G P H I
M
J K M
N
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 22.00.2 20.00.2 20.00.2 22.00.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145 +0.055 -0.045 0.10 1.40.1 0.1250.075 3 +7 -3 1.7 MAX. INCHES 0.8660.008 0.787 +0.009 -0.008 0.787 +0.009 -0.008 0.8660.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.0550.004 0.0050.003 3 +7 -3 0.067 MAX. S144GJ-50-8EU-2
120
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
18. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 18-1. Surface Mounting Type Soldering Conditions
PD703100GJ-40-8EU PD703100GJ-33-8EU
: 144-pin plastic LQFP (fine pitch) (20 x 20 mm) : 144-pin plastic LQFP (fine pitch) (20 x 20 mm)
PD703101GJ-33-xxx-8EU : 144-pin plastic LQFP (fine pitch) (20 x 20 mm) PD703102GJ-33-xxx-8EU : 144-pin plastic LQFP (fine pitch) (20 x 20 mm)
Recommended Condition Symbol IR35-103-2
Soldering Method
Soldering Conditions
Infrared reflow
Package peak temperature: 235C, Time: 30 sec. Max. (at 210C or higher), Count: Note two times or less, Exposure limit: 3 days (after that, prebake at 125C for 10 hours) Pin temperature: 300C Max., Time: 3 sec. Max. (per pin row)
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
Preliminary Data Sheet U13995EJ1V0DS00
121
PD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
122
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Related Documents
PD70F3102-33 Data Sheet (U13844E) PD703100-A33, PD703100-A40, PD703101-A33, PD703102-A33 Data Sheet (To be
prepared)
PD70F3102-A33 Data Sheet (U13845E)
V850 Family Application Note Flash Memory Self-Programming Library (U13261E) Reference Materials: Electrical Characteristics for Microcomputer (IEI-601 Note This document number is that of Japanese version. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. V850E/MS1 Family and V850 are trademarks of NEC Corporation.
Note
)
Preliminary Data Sheet U13995EJ1V0DS00
123
PD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
124
Preliminary Data Sheet U13995EJ1V0DS00
PD703100-33, 703100-40, 703101-33, 703102-33
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Preliminary Data Sheet U13995EJ1V0DS00
125
PD703100-33, 703100-40, 703101-33,
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Lisence not needed
: PD703100-33, 703100-40
The customer must judge the need for lisence : PD703101-33, 703102-33
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
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